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* arch/arc: explicitly set "max-page-size" for GNU LDGravatar Alexey Brodkin2019-12-251-3/+6
| | | | | | | | | | | | | | | | | | | | | | Back in the day we relied on a default value that used to be 8KiB and it worked perfectly fine for ARC's default 8KiB page as well as 4 KiB ones, but not for 16 KiB, see [1] for more details. So that we fixed by setting "max-page-size" if 16KiB pages are in use by commit d024d369b82d2 ("arch/arc: Accommodate 16 KiB MMU pages"). But as Yann very rightfully mentioned here [2] we should be setting this thing explicitly for all page sizes because: 1. Defaults might change unexpectedly 2. Explicitly set stuff is better understood 3. We act similarly to all settings but not only addressing some corner cases [1] https://git.buildroot.org/buildroot/commit/?id=d024d369b82d2d3d9d4d75489c19e9488202bca0 [2] https://patchwork.ozlabs.org/patch/1212544/#2330647 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Yann E. MORIN <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arc: Accommodate 16 KiB MMU pagesGravatar Alexey Brodkin2019-12-221-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARC processors are known for its configurability and one of those configurable things is MMU page size which might be set to any power of two from 4 KiB to 16 MiB, though in the Linux kernel we only support 4, 8 and 16 KiB due to practical considerations. And the most used setting is 8 KiB thus GNU LD assumes maximum page size is 8 KiB by default and while this works for smaller pages (it's OK to align segments by larger value it will be still peoperly aligned) this breaks execution of user-space apps on HW with larger pages because Elf sections might very well span across allocated pages and thus make executable broken. Simplest example: ------------------------------------>8----------------------------------- $ arc-linux-gcc test.c $ arc-linux-readelf --segments a.out Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align ... LOAD 0x000000 0x00010000 0x00010000 0x003e8 0x003e8 R E 0x2000 <-- See LOAD 0x001f24 0x00013f24 0x00013f24 0x000f0 0x0010c RW 0x2000 ------------------------------------>8----------------------------------- Fortunately we may override default page size settings with "max-page-size" linker option this way: ------------------------------------>8----------------------------------- $ arc-linux-gcc test.c -Wl,-z,max-page-size=16384 $ arc-linux-readelf --segments a.out Elf file type is EXEC (Executable file) Entry point 0x102c4 There are 8 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align ... LOAD 0x000000 0x00010000 0x00010000 0x003e8 0x003e8 R E 0x4000 <-- See LOAD 0x001f24 0x00015f24 0x00015f24 0x000f0 0x0010c RW 0x4000 ------------------------------------>8----------------------------------- Which we implement with that change. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> [yann.morin.1998@free.fr: fix comment: s/8196/8192/] Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
* arch/Config.in.arc: introduce the ARC optimized hs38 variantGravatar Vineet Gupta2019-11-121-8/+15
| | | | | | | This corresponds to -mcu=hs38 with mpy-option=9 (64-bit multiplier) Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/riscv: set the default float ABI based on ISA extensionsGravatar Mark Corbin2019-09-191-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets the default floating point ABI based on the ISA extensions that have been selected rather than defaulting to soft float. For 64-bit: ISA 'D' selects lp64d ISA 'F' selects lp64f Otherwise select lp64 For 32-bit: ISA 'D' selects ilp32d ISA 'F' selects ilp32f Otherwise select ilp32 This change was proposed by Palmer Dabbelt at SiFive. Signed-off-by: Mark Corbin <mark.corbin@embecosm.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* ARC: Add support for ARC HS48 v3.1 processorGravatar Evgeniy Didin2019-08-031-4/+12
| | | | | | | | | | | | | | | | | | | This patch introduces a recently released significant update to ARC HS family: ARC HS48. One of the major ARC HS48 features is dual-issue pipeline which requires a little bit modified instruction scheduling compared to single-issue cores (HS38), thus new "-mcpu/--with-cpu=hs4x". Also to address some peculiarities of early designs based on HS48 we introduced yet another "-mcpu/--with-cpu=hs4x_rel31" which we're going to use as well on some of our development boards. Signed-off-by: Evgeniy Didin <didin@synopsys.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: arc-buildroot@synopsys.com [Peter: fixup check-package warnings] Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* ARC: Add support for ARC HS38 with Quad MAC & FPUGravatar Alexey Brodkin2019-08-011-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | We used to build everything for pretty much baseline ARC HS capable of runnig Linux kernel, which was ARC HS38/48 with MMU and caches. But there's a fully featured ARC HS with additional support for - Dual & quad integer multiply and MAC operations - Double-precision floating-point unit It corresponds to the following ARC HS templates in ARChitect: hs38_slc_full. In fact existing HSDK board uses exactly this configuration in its SoC and this is recommended configuration for Linux use-cases. To make life simpler we have corresponding "-mcpu" and "--with-cpu" options in ARC GCC port so we're going to use it and get binaries built accordingly optimized. And while at it added help message so users may better understand what they are dealing with. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
* arch/csky: restrict ck610 to the C-SKY gcc portGravatar Yann E. MORIN2019-08-012-0/+5
| | | | | | | | | | | | | | | | | | | | | | | As Guo explained, upstream gcc does not support abi-v1 (only abi-v2), but ck610 needs abi-v1 [0] [1] To simplify things, we make the whole C-SKY architecture require gcc-9 or later, and add a single exception in gcc to force the ck610 to use the C-SKY port. Note that this does not change the default gcc version to be used for C-SKY: the C-SKY port is still always the default one; the gcc-9 version is only proposed as an alternative (except for ck610, of course). [0] http://lists.busybox.net/pipermail/buildroot/2019-July/254386.html [1] package/Makefile.in#73 Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr> Cc: Guo Ren <guoren@kernel.org> Cc: Arnout Vandecappelle <arnout@mind.be> Cc: Romain Naour <romain.naour@gmail.com> Acked-by: Guo Ren <guoren@kernel.org> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch/arc: always needs -matomic with atomic extensionsGravatar Yann E. MORIN2019-07-181-0/+4
| | | | | | | | | | | | | | | | | | | As reported by Alexey in: https://patchwork.ozlabs.org/patch/1087480/ https://patchwork.ozlabs.org/patch/1087471/ when BR2_ARC_ATOMIC_EXT is enabled, -matomic needs to always be passed to the compiler to allow atomic instructions to be used. So instead of passing them through the command-line CFLAGS, we enforce them in the toolchain wrapper directly. Reported-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com> Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr> Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Arnout Vandecappelle <arnout@mind.be> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: add two new non-cortex-based armv8.2a coresGravatar Yann E. MORIN2019-07-131-0/+18
| | | | | | | | | | | | | | | | | The Neoverse N1 CPU was supported in GCC earlier through the codename Ares [1]. [1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=37cf0ddecfd1eb5c6852a44135af5a92e5103931 Build tested: https://gitlab.com/kubu93/buildroot/pipelines/60318953 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> [Romain: rename BR2_ares to BR2_neoverse_n1] Signed-off-by: Romain Naour <romain.naour@gmail.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> [Arnout: 'aka' instead of 'alias'] Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
* arch/arm: add two new cortex-based armv8.2a coresGravatar Yann E. MORIN2019-07-131-0/+20
| | | | | | | | | | | | | | | | | | | | | | The cortex-a76 implements the full amrv8.2a extensions, and some optional extensions from the armv8.3a, armv8.4a, and armv8.5a sets, but none of their mandatory extensions, which means that it does not qualify for better than an armv8.2a: https://developer.arm.com/products/processors/cortex-a/cortex-a76 http://infocenter.arm.com/help/topic/com.arm.doc.100798_0301_00_en/giq1479805174793.html http://infocenter.arm.com/help/topic/com.arm.doc.100798_0301_00_en/fjv1477559794375.html Also, gcc fits it in the armv8.2a category, too: https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;h=67ce42fb8aacd4c246295f32151a03b1f318ae44;hb=HEAD#l97 Build tested: https://gitlab.com/kubu93/buildroot/pipelines/60318953 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
* arch/arm: add two new 64-bit-only armv8a coresGravatar Yann E. MORIN2019-07-131-0/+16
| | | | | | | | | | | Build tested: https://gitlab.com/kubu93/buildroot/pipelines/60318953 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
* arch/arm: saphira is in fact an armv8.4aGravatar Yann E. MORIN2019-07-131-2/+2
| | | | | | | | | | | | ... and not an armv8.3a like previously supposed: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=886d991373e4dc5a746d0a33de64f1b36e61eed9 So, change the correspoding labels and comments. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
* arch/arm: some cores have a different name with gcc-9Gravatar Yann E. MORIN2019-07-131-6/+9
| | | | | | | | | | | | | | | | | | | | | | In gcc-9, some cores from the ThunderX familly have been renamed to their marketting names, i.e. OcteonTX. Subsequently, new core names have been added to gcc, with the old names still being around. Update the prompts with the new names as alternative to the existing names. We still keep the kconfig options as-is, so that we do not need to add legacy handling. However, since there is no guarantee for how long gcc will retain compatibility for the older names, we readily switch over to using the new names when using a gcc 9-or-later, but keep using the older names with gcc older than 9. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> [Arnout: don't rely on ordering, but make condition explicit] Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
* arch/arm: move dependency on 64-bit down to individual coresGravatar Yann E. MORIN2019-07-131-8/+14
| | | | | | | | | | | It will make it easier to introduce new variants anywhere in the list, when those variants have different bitness requirements. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
* arch: add BR2_ARCH_NEEDS_GCC_AT_LEAST_9Gravatar Romain Naour2019-06-221-0/+4
| | | | | | | | | | | This new symbol will be used by architectures introduced with gcc 9 and by external toolchains based on gcc 9. [1] https://gcc.gnu.org/gcc-9/changes.html Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/Config.in.nds32: force syntax colouring to kconfigGravatar Yann E. MORIN2019-06-201-0/+3
| | | | | | | | | | | | It is too sad when an editor picks up the wrong syntax... Like was done in e837837791 for all the other archs, force syntax to kconfig for nds32 too. Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr> Cc: Nylon Chen <nylon7@andestech.com> Reviewed-by:Nylon Chen <nylon7@andestech.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: Add support for Westmere targetsGravatar Esben Haabendal2019-06-131-0/+11
| | | | | | | | | The westmere line of x86_64 targets lies between nehalem (corei7) and sandybridge (corei7-avx). Allowing use of -march=westmere enables use of AES instruction set on these targets. Signed-off-by: Esben Haabendal <esben@geanix.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch: Fix typo breaking use of core-avx2 archGravatar Esben Haabendal2019-06-081-1/+1
| | | | | Signed-off-by: Esben Haabendal <esben@geanix.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* Merge branch 'next'Gravatar Peter Korsgaard2019-06-0216-16/+79
|\ | | | | | | Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
| * arch/csky: enable internal toolchain supportGravatar Guo Ren2019-05-311-1/+0
| | | | | | | | | | | | | | | | Now that we have support for C-SKY in gcc, binutils and glibc, we can use Buildroot to build a C-SKY toolchain. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * arch/csky: add support for the ck860 coreGravatar Guo Ren2019-05-312-1/+6
| | | | | | | | | | | | | | | | | | ck860 is newest CPU core of C-SKY with high performance & SMP supported. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * arch/csky: specify BR2_GCC_TARGET_FLOAT_ABIGravatar Guo Ren2019-05-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The C-SKY architecture uses two different ABIs, depending on the core being used: - "abiv1" is a mcore based ISA with ELF_NUM:39 and does not support FPU & VDSP. It is used only for the ck610 core. - "abiv2" is C-SKY's own ISA with ELF_NUM:252 and supports FPU & VDSP. It is used for the ck807, ck810, ck860 cores. Since "abiv1" does not support FPU, BR2_GCC_TARGET_FLOAT_ABI will always have the value "soft" for the ck610 core. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [Thomas: rework commit log] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * arch/csky: add support for VDSP extensionsGravatar Guo Ren2019-05-312-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | VDSP is C-SKY enhanced extension instruction set for SIMD, AI and DSP operation. It is supported by abiv2, used by the ck807, ck810, ck860 cores. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [Thomas: update help text in Config.in.legacy about the BR2_CSKY_DSP option.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * arch/csky: remove BR2_CSKY_DSP optionGravatar Guo Ren2019-05-312-8/+0
| | | | | | | | | | | | | | | | | | | | The DSP extention is in fact no longer used for C-SKY, nor supported by C-SKY gcc, so we remove it. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [Thomas: split from the VDSP patch, add Config.in.legacy] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * arch/csky: move GCC_TARGET_CPU calculation to arch.mk.cskyGravatar Guo Ren2019-05-312-11/+24
| | | | | | | | | | | | | | | | | | | | | | Calculating GCC_TARGET_CPU requires combining multiple flags, which isn't very nicely expressed in Config.in, so let's move this into arch.mk.csky, similarly to what is done in arch.mk.riscv. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [Thomas: rework commit log] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * arch: force syntax colouring to kconfig in Config.in.*Gravatar Yann E. MORIN2019-05-2014-0/+42
| | | | | | | | | | | | | | It is too sad when an editor picks up the wrong syntax... Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* | arch/Config.in.powerpc: remove unused gcc target abi options for powerpcGravatar Romain Naour2019-06-011-8/+0
|/ | | | | | | | | | | | | | | | | | | | | | gcc target abi options for powerpc were added by [1] and renamed by [2] to BR2_PPC_ABI_* but never used. Since always BR2_GCC_TARGET_ABI is empty when using a powerpc toolchain. Buildroot currently support SPE and Classic target ABI, nothing seems to require a specific gcc target abi option. This patch is a cleanup like commit [3]. [1] 7d8a59b40e46fa6ed84a5b78644327e97d04adef [2] 98175bd43dbfc70f473cca6759bc8a2f4e655734 [3] fd08153b9d677d654add6c580b9ccc5c27d672e2 Signed-off-by: Romain Naour <romain.naour@gmail.com> Cc: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Cyril Bur <cyrilbur@gmail.com> Cc: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* package/binutils: fix build error due to architecture name is incompleteGravatar Nylon Chen2019-04-201-1/+1
| | | | | | | | | | Fixes http://autobuild.buildroot.net/results/128/12803a705586e82fdfb49013da2eb3b9879ccd45/ Signed-off-by: Che-Wei Chuang <cnoize@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Signed-off-by: Nylon Chen <nylon7@andestech.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: add support for Andes 32-bit (nds32)Gravatar Nylon Chen2019-04-172-0/+23
| | | | | | | | | | This commit provides basic support for the Andes 32-bit (nds32) architecture. Signed-off-by: Che-Wei Chuang <cnoize@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Signed-off-by: Nylon Chen <nylon7@andestech.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/mips: add (Marvell) Octeon III processorGravatar Thomas De Schampheleire2019-02-041-0/+9
| | | | | | | | | | | | | The compiler recognizes a specific 'march' value for Octeon III processors, so create a 'Target Architecture Variant' entry for it in the target menu. Note: support for '-march=octeon3' was added in gcc 5.x. However, the official compiler provided by Marvell (Cavium Networks) uses gcc 4.7.x (and supports -march=octeon3 via their own modifications). For this reason, no line 'select BR2_ARCH_NEEDS_GCC_AT_LEAST_5' is added. Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/mips: add (Marvell) Octeon II processorGravatar Thomas De Schampheleire2019-02-041-0/+8
| | | | | | | | The compiler recognizes a specific 'march' value for Octeon II processors, so create a 'Target Architecture Variant' entry for it in the target menu. Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/mips: introduce mips32r3 and mips64r3Gravatar Thomas De Schampheleire2019-02-041-2/+18
| | | | | | | | | | | | | It's unclear why Buildroot only defined MIPS 32/64 releases 1, 2, 5 and 6 while 3 exists as well. Interesting fact: "Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures." https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64 Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: add support for RISC-V 32-bit (riscv32) architectureGravatar Mark Corbin2019-01-062-4/+31
| | | | | | | | | | | | | | | | This enables a riscv32 system to be built with a Buildroot generated toolchain (gcc >= 7.x, binutils >= 2.30, glibc only). This requires a custom version of glibc 2.26 from the riscv-glibc repository. Note that there are no tags in this repository, so the glibc version just consists of the 40 character commit id string. Thanks to Fabrice Bellard for pointing me towards the 32-bit glibc repository and for providing the necessary patch to get it to build. Signed-off-by: Mark Corbin <mark.corbin@embecosm.com> Reviewed-by: Matt Weber <matthew.weber@rockwellcollins.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: add an armv8.3a coreGravatar Yann E. MORIN2018-12-301-0/+12
| | | | | | | | | | | | | | The armv8.3a generation is a cumulative extension to armv8.2a. Since gcc correctly enables the appropriate extensions based on the core name, we don't really need to introduce a separate config for armv8.3a, and we can piggyback on armv8a. This new core is AArch64 only. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: add armv8.2a cortex-based coresGravatar Yann E. MORIN2018-12-301-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The armv8.2a generation is a cumulative extension to armv8.1a. Since gcc correctly enables the appropriate extensions based on the core name, we don't really need to introduce a separate config for armv8.2a, and we can piggyback on armv8a. In theory, gcc supports those cores in arm mode. However, configuring gcc thusly generates a non-working gcc that constantly whines: cc1: warning: switch -mcpu=cortex-a55 conflicts with -march=armv8.2-a switch It is to be noted that the -march flag is internal to gcc. It is not something that Buildroot did set when configuring gcc; Buildroot only ever sets --with-cpu (not --with-arch). Additionally, uClibc fails to build entirely (unsure if this is caused by the above, or if it is a separate issue, though), with: #### Your compiler does not support TLS and you are trying to build uClibc-ng #### with NPTL support. Upgrade your binutils and gcc to versions which #### support TLS for your architecture. Do not contact uClibc-ng maintainers #### about this problem. Glibc and musl have not been tested in arm mode, so maybe we could have a toolchain that eventually works (or at least, pretends to be working), but we decided it was not worth the effort. Thus, we restrict those cores to AArch64 mode only. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: restrict more armv8a cores to aarch64Gravatar Yann E. MORIN2018-12-301-7/+1
| | | | | | | | | | | | | Since gcc-8, falkor and qdf24xx have been available only as AArch64. Indeed, according to upstream commit [1], the released HW has never supported AArch32. [1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=96a411453d39e6583fa4d7008761a1977cdbe7fa Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [Thomas: improve commit log] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: drop useless conditional dependencies for 64-bit-only coresGravatar Yann E. MORIN2018-12-301-9/+0
| | | | | | | | | Those cores are already guarded by a 64-bit-only condition, so they can't even select additional options in non-64-bit mode anyway... Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: drop BR2_GCC_TARGET_CPU_REVISION optionGravatar Thomas Petazzoni2018-10-012-4/+0
| | | | | | | | | | | In commit 325bb37942f8d3826dab9dc6e88b25234e67a2cf, support for the Blackfin architecture was removed. This was our only use of BR2_GCC_TARGET_CPU_REVISION, and since this config option somewhat complicates the calculation of the --with-cpu/-mcpu option values, let's drop it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch: add support for RISC-V 64-bit (riscv64) architectureGravatar Mark Corbin2018-09-233-0/+145
| | | | | | | | | | | | | | This enables a riscv64 system to be built with a Buildroot generated toolchain (gcc >= 7.x, binutils >= 2.30, glibc only). This configuration has been used to successfully build a qemu-bootable riscv-linux-4.15 kernel (https://github.com/riscv/riscv-linux.git). Signed-off-by: Mark Corbin <mark.corbin@embecosm.com> [Thomas: - simplify arch.mk.riscv by directly setting GCC_TARGET_ARCH - simplify glibc.mk changes by using GLIBC_CONF_ENV.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arch.mk: fix check-package warningsGravatar Thomas Petazzoni2018-09-231-0/+6
| | | | | | | | | | | | | | | | "make check-package" is not happy with the formatting of the recently introduced arch.mk: arch/arch.mk:1: should be 80 hashes (http://nightly.buildroot.org/#writing-rules-mk) arch/arch.mk:2: should be 1 hash (http://nightly.buildroot.org/#writing-rules-mk) arch/arch.mk:4: should be 1 hash (http://nightly.buildroot.org/#writing-rules-mk) arch/arch.mk:5: should be 80 hashes (http://nightly.buildroot.org/#writing-rules-mk) arch/arch.mk:6: should be a blank line (http://nightly.buildroot.org/#writing-rules-mk) Let's fix this by adding a comment header that makes check-package happy. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: allow GCC target options to be optionally overwrittenGravatar Mark Corbin2018-09-231-0/+17
| | | | | | | | | | | | | The BR2_GCC_TARGET_* configuration variables are copied to corresponding GCC_TARGET_* variables which may then be optionally modified or overwritten by architecture specific makefiles. All makefiles must use the new GCC_TARGET_* variables instead of the BR2_GCC_TARGET_* versions. Signed-off-by: Mark Corbin <mark.corbin@embecosm.com> [Thomas: simplify include of arch/arch.mk] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: drop now useless support for FDPICGravatar Yann E. MORIN2018-07-011-14/+0
| | | | | | | | | | | | Now that we dropped support for blackfin, we no longer have any architecture that supports FDPIC, so BR2_ARCH_HAS_FDPIC_SUPPORT is never selected, so we can't select BR2_BINFMT_FDPIC. Drop all of that now. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: add BR2_ARCH_NEEDS_GCC_AT_LEAST_8Gravatar Romain Naour2018-05-301-0/+4
| | | | | | | | | | | This new symbol will be used by architectures introduced with gcc 8 and by external toolchains based on gcc 8. [1] https://gcc.gnu.org/gcc-8/changes.html Signed-off-by: Romain Naour <romain.naour@gmail.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: cortex-m7 may have a FPv5 FPUGravatar Yann E. MORIN2018-05-201-0/+1
| | | | | Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: cortex-m4 may have an FPv4 FPUGravatar Yann E. MORIN2018-05-201-0/+1
| | | | | Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: add options for FPv5 FPUGravatar Yann E. MORIN2018-05-201-0/+37
| | | | | | | | | | | | | | Contrary to its older brother, the FPv5 comes in two flavours; single- and double-precision [0] [1]. the two variants are only available for cortex-m7 cores, and the two variants are known to gcc as fpv5-sp-d16 and fpv5-d16, respectively, since gcc-5 [2]. [0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M7 [1] https://developer.arm.com/docs/ddi0489/latest/floating-point-unit [2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a076f99fa702deac764f6e0441b9435ad999f521 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: add option for FPv4 FPUGravatar Yann E. MORIN2018-05-201-0/+20
| | | | | | | | | | | | | The FPv4-SP FPU is a single-precision FPU with 16 double registers [0] [1]. It is only available for cortex-m4 cores, and is known to gcc as fpv4-sp-d16 (note that there is no leading 'v') since gcc-4.5 [2]. [0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4 [1] https://developer.arm.com/docs/ddi0439/latest/floating-point-unit [2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=639cb7b789a54bf78d6ae5e2644450f5eb1837a6 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: introduce generic FPU internal optionGravatar Yann E. MORIN2018-05-201-4/+13
| | | | | | | | | | | | | | | | | | | Currently, we consider that any VFP FPU is a superset of VFPv2, and thus we use VFPv2 as a way to detect that a VFP is used. However, for Cortex-M cores, the optional FPU is not a superset of VFPv2; it is even not a VFP [0]. As a consequence, we can no longer consider VFPv2 as a indication that an FPU is present. So, we introduce two new internal options, BR2_ARM_CPU_MAYBE_HAS_FPU and BR2_ARM_CPU_HAS_FPU, which we use to consider the presence of an FPU. [0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch/arm: add cortex-m7 coreGravatar Yann E. MORIN2018-05-201-0/+6
| | | | | | | Nothing fancy, just a plain Cortex-M, armv7-M core... Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* arch: drop BR2_BINFMT_FLAT_SEP_DATA supportGravatar Thomas Petazzoni2018-04-151-12/+0
| | | | | | This was only used by Blackfin, so there's no good reason to keep it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>