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authorPeter Korsgaard <jacmet@sunsite.dk>2011-08-26 05:13:33 (GMT)
committer Peter Korsgaard <jacmet@sunsite.dk>2011-08-26 05:16:23 (GMT)
commitcb6c2c427838a0ba5dc7bb404734574c9ed6b102 (patch)
tree1976eadee6a8ebce15bbc578955eef207ffa026e
parentd881a14f9b7e7367bc664105bd98166015eaefaf (diff)
downloadbuildroot-cb6c2c427838a0ba5dc7bb404734574c9ed6b102.tar.gz
buildroot-cb6c2c427838a0ba5dc7bb404734574c9ed6b102.tar.bz2
grub: fix patch handling after AUTOTARGETS conversion
Closes #4093 AUTOTARGETS doesn't handle compressed patches, so the '400' patch did not get applied. Fix it by extracting the patch. With this, the '500' patch is no longer needed. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
-rw-r--r--CHANGES4
-rw-r--r--boot/grub/grub.400-nic_update2.patch49480
-rw-r--r--boot/grub/grub.400-nic_update2.patch.bz2bin328903 -> 0 bytes
-rw-r--r--boot/grub/grub.500-build-fix.patch14
4 files changed, 49484 insertions, 14 deletions
diff --git a/CHANGES b/CHANGES
index 1e5ea4e..2b64c33 100644
--- a/CHANGES
+++ b/CHANGES
@@ -10,6 +10,10 @@
libxml-parser-perl, mtd, python, ti-utils, udev, usbmount,
util-linux, xfont_font-misc-misc
+ Issues resolved (http://bugs.uclibc.org):
+
+ #4093: Grub fails to install bz2 patch after conversion to...
+
2011.08-rc1, Released August 4th, 2011:
Fixes all over the tree and new features.
diff --git a/boot/grub/grub.400-nic_update2.patch b/boot/grub/grub.400-nic_update2.patch
new file mode 100644
index 0000000..064c953
--- /dev/null
+++ b/boot/grub/grub.400-nic_update2.patch
@@ -0,0 +1,49480 @@
+Submitted By: Jim Gifford (patches at jg555 dot com)
+Date: 2005-08-31
+Initial Package Version: 0.97
+Origin: OpenSolaris, Joe Ciccone, Jim Gifford
+Upstream Status: N/A
+Description: Adds support for Forcedeth and other NIC's
+ Fixes for GCC 4.x
+ Removal of bad network drivers
+
+diff -Naur grub-0.97.orig/configure grub-0.97/configure
+--- grub-0.97.orig/configure 2005-05-08 02:48:12.000000000 +0000
++++ grub-0.97/configure 2005-09-01 00:15:48.000000000 +0000
+@@ -872,47 +872,32 @@
+ --disable-packet-retransmission
+ turn off packet retransmission
+ --enable-pci-direct access PCI directly instead of using BIOS
+- --enable-3c509 enable 3Com509 driver
+- --enable-3c529 enable 3Com529 driver
+ --enable-3c595 enable 3Com595 driver
+ --enable-3c90x enable 3Com90x driver
+- --enable-cs89x0 enable CS89x0 driver
+ --enable-davicom enable Davicom driver
+- --enable-depca enable DEPCA and EtherWORKS driver
+- --enable-eepro enable Etherexpress Pro/10 driver
++ --enable-e1000 enable Etherexpress Pro/1000 driver
+ --enable-eepro100 enable Etherexpress Pro/100 driver
+ --enable-epic100 enable SMC 83c170 EPIC/100 driver
+- --enable-3c507 enable 3Com507 driver
+- --enable-exos205 enable EXOS205 driver
+- --enable-ni5210 enable Racal-Interlan NI5210 driver
+- --enable-lance enable Lance PCI PCNet/32 driver
+- --enable-ne2100 enable Novell NE2100 driver
+- --enable-ni6510 enable Racal-Interlan NI6510 driver
++ --enable-forcedeth enable Nvidia Geforce driver
+ --enable-natsemi enable NatSemi DP8381x driver
+- --enable-ni5010 enable Racal-Interlan NI5010 driver
+- --enable-3c503 enable 3Com503 driver
+- --enable-ne enable NE1000/2000 ISA driver
++ --enable-ns83820 enable NS83820 driver
+ --enable-ns8390 enable NE2000 PCI driver
+- --enable-wd enable WD8003/8013, SMC8216/8416 driver
+- --enable-otulip enable old Tulip driver
++ --enable-pcnet32 enable AMD Lance/PCI PCNet/32 driver
++ --enable-pnic enable Bochs Pseudo Nic driver
+ --enable-rtl8139 enable Realtek 8139 driver
++ --enable-r8169 enable Realtek 8169 driver
+ --enable-sis900 enable SIS 900 and SIS 7016 driver
+- --enable-sk-g16 enable Schneider and Koch G16 driver
+- --enable-smc9000 enable SMC9000 driver
+- --enable-tiara enable Tiara driver
++ --enable-tg3 enable Broadcom Tigon3 driver
+ --enable-tulip enable Tulip driver
++ --enable-tlan enable TI ThunderLAN driver
++ --enable-undi enable PXE UNDI driver
+ --enable-via-rhine enable Rhine-I/II driver
+- --enable-w89c840 enable Winbond W89c840, Compex RL100-ATX driver
+- --enable-3c503-shmem use 3c503 shared memory mode
+- --enable-3c503-aui use AUI by default on 3c503 cards
++ --enable-w89c840 enable Winbond W89c840 driver
+ --enable-compex-rl2000-fix
+ specify this if you have a Compex RL2000 PCI
+- --enable-smc9000-scan=LIST
+- probe for SMC9000 I/O addresses using LIST
+ --enable-ne-scan=LIST probe for NE base address using LIST
+ --enable-wd-default-mem=MEM
+ set the default memory location for WD/SMC
+- --enable-cs-scan=LIST probe for CS89x0 base address using LIST
+ --enable-diskless enable diskless support
+ --disable-hercules disable hercules terminal support
+ --disable-serial disable serial terminal support
+@@ -5559,7 +5544,7 @@
+
+ fi;
+ if test "x$enable_packet_retransmission" != xno; then
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCONGESTED=1"
++ NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCONGESTED=1 -DCONFIG_PCI"
+ fi
+
+ # Check whether --enable-pci-direct or --disable-pci-direct was given.
+@@ -5571,26 +5556,6 @@
+ NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCONFIG_PCI_DIRECT=1"
+ fi
+
+-# Check whether --enable-3c509 or --disable-3c509 was given.
+-if test "${enable_3c509+set}" = set; then
+- enableval="$enable_3c509"
+-
+-fi;
+-if test "x$enable_3c509" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C509"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c509.o"
+-fi
+-
+-# Check whether --enable-3c529 or --disable-3c529 was given.
+-if test "${enable_3c529+set}" = set; then
+- enableval="$enable_3c529"
+-
+-fi;
+-if test "x$enable_3c529" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C529=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c529.o"
+-fi
+-
+ # Check whether --enable-3c595 or --disable-3c595 was given.
+ if test "${enable_3c595+set}" = set; then
+ enableval="$enable_3c595"
+@@ -5611,16 +5576,6 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c90x.o"
+ fi
+
+-# Check whether --enable-cs89x0 or --disable-cs89x0 was given.
+-if test "${enable_cs89x0+set}" = set; then
+- enableval="$enable_cs89x0"
+-
+-fi;
+-if test "x$enable_cs89x0" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_CS89X0=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS cs89x0.o"
+-fi
+-
+ # Check whether --enable-davicom or --disable-davicom was given.
+ if test "${enable_davicom+set}" = set; then
+ enableval="$enable_davicom"
+@@ -5631,24 +5586,14 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS davicom.o"
+ fi
+
+-# Check whether --enable-depca or --disable-depca was given.
+-if test "${enable_depca+set}" = set; then
+- enableval="$enable_depca"
++# Check whether --enable-e1000 or --disable-e1000 was given.
++if test "${enable_e1000+set}" = set; then
++ enableval="$enable_e1000"
+
+ fi;
+-if test "x$enable_depca" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_DEPCA=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS depca.o"
+-fi
+-
+-# Check whether --enable-eepro or --disable-eepro was given.
+-if test "${enable_eepro+set}" = set; then
+- enableval="$enable_eepro"
+-
+-fi;
+-if test "x$enable_eepro" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_EEPRO=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS eepro.o"
++if test "x$enable_e1000" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_E1000=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS e1000.o"
+ fi
+
+ # Check whether --enable-eepro100 or --disable-eepro100 was given.
+@@ -5671,64 +5616,14 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS epic100.o"
+ fi
+
+-# Check whether --enable-3c507 or --disable-3c507 was given.
+-if test "${enable_3c507+set}" = set; then
+- enableval="$enable_3c507"
+-
+-fi;
+-if test "x$enable_3c507" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C507=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c507.o"
+-fi
+-
+-# Check whether --enable-exos205 or --disable-exos205 was given.
+-if test "${enable_exos205+set}" = set; then
+- enableval="$enable_exos205"
+-
+-fi;
+-if test "x$enable_exos205" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_EXOS205=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS exos205.o"
+-fi
+-
+-# Check whether --enable-ni5210 or --disable-ni5210 was given.
+-if test "${enable_ni5210+set}" = set; then
+- enableval="$enable_ni5210"
+-
+-fi;
+-if test "x$enable_ni5210" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NI5210=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ni5210.o"
+-fi
+-
+-# Check whether --enable-lance or --disable-lance was given.
+-if test "${enable_lance+set}" = set; then
+- enableval="$enable_lance"
+-
+-fi;
+-if test "x$enable_lance" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_LANCE=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS lance.o"
+-fi
+-
+-# Check whether --enable-ne2100 or --disable-ne2100 was given.
+-if test "${enable_ne2100+set}" = set; then
+- enableval="$enable_ne2100"
+-
+-fi;
+-if test "x$enable_ne2100" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NE2100=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ne2100.o"
+-fi
+-
+-# Check whether --enable-ni6510 or --disable-ni6510 was given.
+-if test "${enable_ni6510+set}" = set; then
+- enableval="$enable_ni6510"
++# Check whether --enable-forcedeth or --disable-forcedeth was given.
++if test "${enable_forcedeth+set}" = set; then
++ enableval="$enable_forcedeth"
+
+ fi;
+-if test "x$enable_ni6510" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NI6510=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ni6510.o"
++if test "x$enable_forcedeth" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_FORCEDETH=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS forcedeth.o"
+ fi
+
+ # Check whether --enable-natsemi or --disable-natsemi was given.
+@@ -5741,34 +5636,14 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS natsemi.o"
+ fi
+
+-# Check whether --enable-ni5010 or --disable-ni5010 was given.
+-if test "${enable_ni5010+set}" = set; then
+- enableval="$enable_ni5010"
++# Check whether --enable-ns83820 or --disable-ns83820 was given.
++if test "${enable_ns83820+set}" = set; then
++ enableval="$enable_ns83820"
+
+ fi;
+-if test "x$enable_ni5010" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NI5010=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ni5010.o"
+-fi
+-
+-# Check whether --enable-3c503 or --disable-3c503 was given.
+-if test "${enable_3c503+set}" = set; then
+- enableval="$enable_3c503"
+-
+-fi;
+-if test "x$enable_3c503" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C503=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c503.o"
+-fi
+-
+-# Check whether --enable-ne or --disable-ne was given.
+-if test "${enable_ne+set}" = set; then
+- enableval="$enable_ne"
+-
+-fi;
+-if test "x$enable_ne" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NE=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ne.o"
++if test "x$enable_ns83820" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NS83820=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS ns83820.o"
+ fi
+
+ # Check whether --enable-ns8390 or --disable-ns8390 was given.
+@@ -5781,24 +5656,24 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS ns8390.o"
+ fi
+
+-# Check whether --enable-wd or --disable-wd was given.
+-if test "${enable_wd+set}" = set; then
+- enableval="$enable_wd"
++# Check whether --enable-pcnet32 or --disable-pcnet32 was given.
++if test "${enable_pcnet32+set}" = set; then
++ enableval="$enable_pcnet32"
+
+ fi;
+-if test "x$enable_wd" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_WD=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS wd.o"
++if test "x$enable_pcnet32" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_PCNET32=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS pcnet32.o"
+ fi
+
+-# Check whether --enable-otulip or --disable-otulip was given.
+-if test "${enable_otulip+set}" = set; then
+- enableval="$enable_otulip"
++# Check whether --enable-pnic or --disable-pnic was given.
++if test "${enable_pnic+set}" = set; then
++ enableval="$enable_pnic"
+
+ fi;
+-if test "x$enable_otulip" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_OTULIP=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS otulip.o"
++if test "x$enable_pnic" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_PNIC=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS pnic.o"
+ fi
+
+ # Check whether --enable-rtl8139 or --disable-rtl8139 was given.
+@@ -5811,6 +5686,16 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS rtl8139.o"
+ fi
+
++# Check whether --enable-r8169 or --disable-r8169 was given.
++if test "${enable_r8169+set}" = set; then
++ enableval="$enable_r8169"
++
++fi;
++if test "x$enable_r8169" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_R8169=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS r8169.o"
++fi
++
+ # Check whether --enable-sis900 or --disable-sis900 was given.
+ if test "${enable_sis900+set}" = set; then
+ enableval="$enable_sis900"
+@@ -5821,34 +5706,14 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS sis900.o"
+ fi
+
+-# Check whether --enable-sk-g16 or --disable-sk-g16 was given.
+-if test "${enable_sk_g16+set}" = set; then
+- enableval="$enable_sk_g16"
+-
+-fi;
+-if test "x$enable_sk_g16" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_SK_G16=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS sk_g16.o"
+-fi
+-
+-# Check whether --enable-smc9000 or --disable-smc9000 was given.
+-if test "${enable_smc9000+set}" = set; then
+- enableval="$enable_smc9000"
+-
+-fi;
+-if test "x$enable_smc9000" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_SMC9000=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS smc9000.o"
+-fi
+-
+-# Check whether --enable-tiara or --disable-tiara was given.
+-if test "${enable_tiara+set}" = set; then
+- enableval="$enable_tiara"
++# Check whether --enable-tg3 or --disable-tg3 was given.
++if test "${enable_tg3+set}" = set; then
++ enableval="$enable_tg3"
+
+ fi;
+-if test "x$enable_tiara" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_TIARA=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS tiara.o"
++if test "x$enable_tg3" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_TG3=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS tg3.o"
+ fi
+
+ # Check whether --enable-tulip or --disable-tulip was given.
+@@ -5861,6 +5726,16 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS tulip.o"
+ fi
+
++# Check whether --enable-tlan or --disable-tlan was given.
++if test "${enable_tlan+set}" = set; then
++ enableval="$enable_tlan"
++
++fi;
++if test "x$enable_tlan" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_TLAN=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS tlan.o"
++fi
++
+ # Check whether --enable-via-rhine or --disable-via-rhine was given.
+ if test "${enable_via_rhine+set}" = set; then
+ enableval="$enable_via_rhine"
+@@ -5895,24 +5770,6 @@
+ FSYS_CFLAGS="$FSYS_CFLAGS -DFSYS_TFTP=1"
+ fi
+
+-# Check whether --enable-3c503-shmem or --disable-3c503-shmem was given.
+-if test "${enable_3c503_shmem+set}" = set; then
+- enableval="$enable_3c503_shmem"
+-
+-fi;
+-if test "x$enable_3c503_shmem" = xyes; then
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DT503_SHMEM=1"
+-fi
+-
+-# Check whether --enable-3c503-aui or --disable-3c503-aui was given.
+-if test "${enable_3c503_aui+set}" = set; then
+- enableval="$enable_3c503_aui"
+-
+-fi;
+-if test "x$enable_3c503_aui" = xyes; then
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DT503_AUI=1"
+-fi
+-
+ # Check whether --enable-compex-rl2000-fix or --disable-compex-rl2000-fix was given.
+ if test "${enable_compex_rl2000_fix+set}" = set; then
+ enableval="$enable_compex_rl2000_fix"
+@@ -5922,12 +5779,6 @@
+ NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCOMPEX_RL2000_FIX=1"
+ fi
+
+-# Check whether --enable-smc9000-scan or --disable-smc9000-scan was given.
+-if test "${enable_smc9000_scan+set}" = set; then
+- enableval="$enable_smc9000_scan"
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DSMC9000_SCAN=$enable_smc9000_scan"
+-fi;
+-
+ # Check whether --enable-ne-scan or --disable-ne-scan was given.
+ if test "${enable_ne_scan+set}" = set; then
+ enableval="$enable_ne_scan"
+@@ -5944,12 +5795,6 @@
+ NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DWD_DEFAULT_MEM=0xCC000"
+ fi;
+
+-# Check whether --enable-cs-scan or --disable-cs-scan was given.
+-if test "${enable_cs_scan+set}" = set; then
+- enableval="$enable_cs_scan"
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCS_SCAN=$enable_cs_scan"
+-fi;
+-
+ # Check whether --enable-diskless or --disable-diskless was given.
+ if test "${enable_diskless+set}" = set; then
+ enableval="$enable_diskless"
+diff -Naur grub-0.97.orig/configure.ac grub-0.97/configure.ac
+--- grub-0.97.orig/configure.ac 2005-05-08 02:36:03.000000000 +0000
++++ grub-0.97/configure.ac 2005-09-01 00:16:05.000000000 +0000
+@@ -317,7 +317,7 @@
+ [ --disable-packet-retransmission
+ turn off packet retransmission])
+ if test "x$enable_packet_retransmission" != xno; then
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCONGESTED=1"
++ NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCONGESTED=1 -DCONFIG_PCI"
+ fi
+
+ AC_ARG_ENABLE(pci-direct,
+@@ -327,20 +327,6 @@
+ fi
+
+ dnl Device drivers.
+-AC_ARG_ENABLE(3c509,
+- [ --enable-3c509 enable 3Com509 driver])
+-if test "x$enable_3c509" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C509"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c509.o"
+-fi
+-
+-AC_ARG_ENABLE(3c529,
+- [ --enable-3c529 enable 3Com529 driver])
+-if test "x$enable_3c529" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C529=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c529.o"
+-fi
+-
+ AC_ARG_ENABLE(3c595,
+ [ --enable-3c595 enable 3Com595 driver])
+ if test "x$enable_3c595" = xyes; then
+@@ -355,13 +341,6 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c90x.o"
+ fi
+
+-AC_ARG_ENABLE(cs89x0,
+- [ --enable-cs89x0 enable CS89x0 driver])
+-if test "x$enable_cs89x0" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_CS89X0=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS cs89x0.o"
+-fi
+-
+ AC_ARG_ENABLE(davicom,
+ [ --enable-davicom enable Davicom driver])
+ if test "x$enable_davicom" = xyes; then
+@@ -369,18 +348,11 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS davicom.o"
+ fi
+
+-AC_ARG_ENABLE(depca,
+- [ --enable-depca enable DEPCA and EtherWORKS driver])
+-if test "x$enable_depca" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_DEPCA=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS depca.o"
+-fi
+-
+-AC_ARG_ENABLE(eepro,
+- [ --enable-eepro enable Etherexpress Pro/10 driver])
+-if test "x$enable_eepro" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_EEPRO=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS eepro.o"
++AC_ARG_ENABLE(e1000,
++ [ --enable-e1000 enable Etherexpress Pro/1000 driver])
++if test "x$enable_e1000" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_E1000=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS e1000.o"
+ fi
+
+ AC_ARG_ENABLE(eepro100,
+@@ -397,46 +369,11 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS epic100.o"
+ fi
+
+-AC_ARG_ENABLE(3c507,
+- [ --enable-3c507 enable 3Com507 driver])
+-if test "x$enable_3c507" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C507=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c507.o"
+-fi
+-
+-AC_ARG_ENABLE(exos205,
+- [ --enable-exos205 enable EXOS205 driver])
+-if test "x$enable_exos205" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_EXOS205=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS exos205.o"
+-fi
+-
+-AC_ARG_ENABLE(ni5210,
+- [ --enable-ni5210 enable Racal-Interlan NI5210 driver])
+-if test "x$enable_ni5210" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NI5210=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ni5210.o"
+-fi
+-
+-AC_ARG_ENABLE(lance,
+- [ --enable-lance enable Lance PCI PCNet/32 driver])
+-if test "x$enable_lance" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_LANCE=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS lance.o"
+-fi
+-
+-AC_ARG_ENABLE(ne2100,
+- [ --enable-ne2100 enable Novell NE2100 driver])
+-if test "x$enable_ne2100" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NE2100=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ne2100.o"
+-fi
+-
+-AC_ARG_ENABLE(ni6510,
+- [ --enable-ni6510 enable Racal-Interlan NI6510 driver])
+-if test "x$enable_ni6510" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NI6510=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ni6510.o"
++AC_ARG_ENABLE(forcedeth,
++ [ --enable-forcedeth enable Nvidia Geforce driver])
++if test "x$enable_forcedeth" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_FORCEDETH=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS forcedeth.o"
+ fi
+
+ AC_ARG_ENABLE(natsemi,
+@@ -446,25 +383,11 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS natsemi.o"
+ fi
+
+-AC_ARG_ENABLE(ni5010,
+- [ --enable-ni5010 enable Racal-Interlan NI5010 driver])
+-if test "x$enable_ni5010" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NI5010=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ni5010.o"
+-fi
+-
+-AC_ARG_ENABLE(3c503,
+- [ --enable-3c503 enable 3Com503 driver])
+-if test "x$enable_3c503" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_3C503=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS 3c503.o"
+-fi
+-
+-AC_ARG_ENABLE(ne,
+- [ --enable-ne enable NE1000/2000 ISA driver])
+-if test "x$enable_ne" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NE=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS ne.o"
++AC_ARG_ENABLE(ns83820,
++ [ --enable-ns83820 enable NS83820 driver])
++if test "x$enable_ns83820" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_NS83820=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS ns83820.o"
+ fi
+
+ AC_ARG_ENABLE(ns8390,
+@@ -474,18 +397,18 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS ns8390.o"
+ fi
+
+-AC_ARG_ENABLE(wd,
+- [ --enable-wd enable WD8003/8013, SMC8216/8416 driver])
+-if test "x$enable_wd" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_WD=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS wd.o"
++AC_ARG_ENABLE(pcnet32,
++ [ --enable-pcnet32 enable AMD Lance/PCI PCNet/32 driver])
++if test "x$enable_pcnet32" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_PCNET32=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS pcnet32.o"
+ fi
+
+-AC_ARG_ENABLE(otulip,
+- [ --enable-otulip enable old Tulip driver])
+-if test "x$enable_otulip" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_OTULIP=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS otulip.o"
++AC_ARG_ENABLE(pnic,
++ [ --enable-pnic enable Bochs Pseudo Nic driver])
++if test "x$enable_pnic" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_PNIC=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS pnic.o"
+ fi
+
+ AC_ARG_ENABLE(rtl8139,
+@@ -495,6 +418,13 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS rtl8139.o"
+ fi
+
++AC_ARG_ENABLE(r8169,
++ [ --enable-r8169 enable Realtek 8169 driver])
++if test "x$enable_r8169" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_R8169=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS r8169.o"
++fi
++
+ AC_ARG_ENABLE(sis900,
+ [ --enable-sis900 enable SIS 900 and SIS 7016 driver])
+ if test "x$enable_sis900" = xyes; then
+@@ -502,25 +432,11 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS sis900.o"
+ fi
+
+-AC_ARG_ENABLE(sk-g16,
+- [ --enable-sk-g16 enable Schneider and Koch G16 driver])
+-if test "x$enable_sk_g16" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_SK_G16=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS sk_g16.o"
+-fi
+-
+-AC_ARG_ENABLE(smc9000,
+- [ --enable-smc9000 enable SMC9000 driver])
+-if test "x$enable_smc9000" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_SMC9000=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS smc9000.o"
+-fi
+-
+-AC_ARG_ENABLE(tiara,
+- [ --enable-tiara enable Tiara driver])
+-if test "x$enable_tiara" = xyes; then
+- NET_CFLAGS="$NET_CFLAGS -DINCLUDE_TIARA=1"
+- NETBOOT_DRIVERS="$NETBOOT_DRIVERS tiara.o"
++AC_ARG_ENABLE(tg3,
++ [ --enable-tg3 enable Broadcom Tigon3 driver])
++if test "x$enable_tg3" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_TG3=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS tg3.o"
+ fi
+
+ AC_ARG_ENABLE(tulip,
+@@ -530,6 +446,13 @@
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS tulip.o"
+ fi
+
++AC_ARG_ENABLE(tlan,
++ [ --enable-tlan enable TI ThunderLAN driver])
++if test "x$enable_tlan" = xyes; then
++ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_TLAN=1"
++ NETBOOT_DRIVERS="$NETBOOT_DRIVERS tlan.o"
++fi
++
+ AC_ARG_ENABLE(via-rhine,
+ [ --enable-via-rhine enable Rhine-I/II driver])
+ if test "x$enable_via_rhine" = xyes; then
+@@ -538,7 +461,7 @@
+ fi
+
+ AC_ARG_ENABLE(w89c840,
+- [ --enable-w89c840 enable Winbond W89c840, Compex RL100-ATX driver])
++ [ --enable-w89c840 enable Winbond W89c840 driver])
+ if test "x$enable_w89c840" = xyes; then
+ NET_CFLAGS="$NET_CFLAGS -DINCLUDE_W89C840=1"
+ NETBOOT_DRIVERS="$NETBOOT_DRIVERS w89c840.o"
+@@ -550,19 +473,7 @@
+ FSYS_CFLAGS="$FSYS_CFLAGS -DFSYS_TFTP=1"
+ fi
+
+-dnl Extra options.
+-AC_ARG_ENABLE(3c503-shmem,
+- [ --enable-3c503-shmem use 3c503 shared memory mode])
+-if test "x$enable_3c503_shmem" = xyes; then
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DT503_SHMEM=1"
+-fi
+-
+-AC_ARG_ENABLE(3c503-aui,
+- [ --enable-3c503-aui use AUI by default on 3c503 cards])
+-if test "x$enable_3c503_aui" = xyes; then
+- NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DT503_AUI=1"
+-fi
+-
++dnl extra flag for ns8390.c
+ AC_ARG_ENABLE(compex-rl2000-fix,
+ [ --enable-compex-rl2000-fix
+ specify this if you have a Compex RL2000 PCI])
+@@ -570,11 +481,6 @@
+ NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCOMPEX_RL2000_FIX=1"
+ fi
+
+-AC_ARG_ENABLE(smc9000-scan,
+- [ --enable-smc9000-scan=LIST
+- probe for SMC9000 I/O addresses using LIST],
+- [NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DSMC9000_SCAN=$enable_smc9000_scan"])
+-
+ AC_ARG_ENABLE(ne-scan,
+ [ --enable-ne-scan=LIST probe for NE base address using LIST],
+ [NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DNE_SCAN=$enable_ne_scan"],
+@@ -586,10 +492,6 @@
+ [NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DWD_DEFAULT_MEM=$enable_wd_default_mem"],
+ [NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DWD_DEFAULT_MEM=0xCC000"])
+
+-AC_ARG_ENABLE(cs-scan,
+- [ --enable-cs-scan=LIST probe for CS89x0 base address using LIST],
+- [NET_EXTRAFLAGS="$NET_EXTRAFLAGS -DCS_SCAN=$enable_cs_scan"])
+-
+ dnl Diskless
+ AC_ARG_ENABLE(diskless,
+ [ --enable-diskless enable diskless support])
+diff -Naur grub-0.97.orig/netboot/3c509.h grub-0.97/netboot/3c509.h
+--- grub-0.97.orig/netboot/3c509.h 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/3c509.h 1970-01-01 00:00:00.000000000 +0000
+@@ -1,397 +0,0 @@
+-/*
+- * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are
+- * met: 1. Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer. 2. The name
+- * of the author may not be used to endorse or promote products derived from
+- * this software withough specific prior written permission
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+- *
+- * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
+- *
+- October 2, 1994
+-
+- Modified by: Andres Vega Garcia
+-
+- INRIA - Sophia Antipolis, France
+- e-mail: avega@sophia.inria.fr
+- finger: avega@pax.inria.fr
+-
+- */
+-
+-/*
+- * Ethernet software status per interface.
+- */
+-/*
+- * Some global constants
+- */
+-
+-#define TX_INIT_RATE 16
+-#define TX_INIT_MAX_RATE 64
+-#define RX_INIT_LATENCY 64
+-#define RX_INIT_EARLY_THRESH 64
+-#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
+-#define MIN_RX_EARLY_THRESHL 4
+-
+-#define EEPROMSIZE 0x40
+-#define MAX_EEPROMBUSY 1000
+-#define EP_LAST_TAG 0xd7
+-#define EP_MAX_BOARDS 16
+-#define EP_ID_PORT 0x100
+-
+-/*
+- * some macros to acces long named fields
+- */
+-#define IS_BASE (eth_nic_base)
+-#define BASE (eth_nic_base)
+-
+-/*
+- * Commands to read/write EEPROM trough EEPROM command register (Window 0,
+- * Offset 0xa)
+- */
+-#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
+-#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
+-#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
+-#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
+-
+-#define EEPROM_BUSY (1<<15)
+-#define EEPROM_TST_MODE (1<<14)
+-
+-/*
+- * Some short functions, worth to let them be a macro
+- */
+-#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
+-#define GO_WINDOW(x) outw(WINDOW_SELECT|(x), BASE+EP_COMMAND)
+-
+-/**************************************************************************
+- *
+- * These define the EEPROM data structure. They are used in the probe
+- * function to verify the existance of the adapter after having sent
+- * the ID_Sequence.
+- *
+- * There are others but only the ones we use are defined here.
+- *
+- **************************************************************************/
+-
+-#define EEPROM_NODE_ADDR_0 0x0 /* Word */
+-#define EEPROM_NODE_ADDR_1 0x1 /* Word */
+-#define EEPROM_NODE_ADDR_2 0x2 /* Word */
+-#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
+-#define EEPROM_MFG_ID 0x7 /* 0x6d50 */
+-#define EEPROM_ADDR_CFG 0x8 /* Base addr */
+-#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
+-
+-/**************************************************************************
+- *
+- * These are the registers for the 3Com 3c509 and their bit patterns when
+- * applicable. They have been taken out the the "EtherLink III Parallel
+- * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
+- * from 3com.
+- *
+- **************************************************************************/
+-
+-#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a
+- * command reg. */
+-#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status
+- * reg. */
+-#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window
+- * reg. */
+-/*
+- * Window 0 registers. Setup.
+- */
+-/* Write */
+-#define EP_W0_EEPROM_DATA 0x0c
+-#define EP_W0_EEPROM_COMMAND 0x0a
+-#define EP_W0_RESOURCE_CFG 0x08
+-#define EP_W0_ADDRESS_CFG 0x06
+-#define EP_W0_CONFIG_CTRL 0x04
+-/* Read */
+-#define EP_W0_PRODUCT_ID 0x02
+-#define EP_W0_MFG_ID 0x00
+-
+-/*
+- * Window 1 registers. Operating Set.
+- */
+-/* Write */
+-#define EP_W1_TX_PIO_WR_2 0x02
+-#define EP_W1_TX_PIO_WR_1 0x00
+-/* Read */
+-#define EP_W1_FREE_TX 0x0c
+-#define EP_W1_TX_STATUS 0x0b /* byte */
+-#define EP_W1_TIMER 0x0a /* byte */
+-#define EP_W1_RX_STATUS 0x08
+-#define EP_W1_RX_PIO_RD_2 0x02
+-#define EP_W1_RX_PIO_RD_1 0x00
+-
+-/*
+- * Window 2 registers. Station Address Setup/Read
+- */
+-/* Read/Write */
+-#define EP_W2_ADDR_5 0x05
+-#define EP_W2_ADDR_4 0x04
+-#define EP_W2_ADDR_3 0x03
+-#define EP_W2_ADDR_2 0x02
+-#define EP_W2_ADDR_1 0x01
+-#define EP_W2_ADDR_0 0x00
+-
+-/*
+- * Window 3 registers. FIFO Management.
+- */
+-/* Read */
+-#define EP_W3_FREE_TX 0x0c
+-#define EP_W3_FREE_RX 0x0a
+-
+-/*
+- * Window 4 registers. Diagnostics.
+- */
+-/* Read/Write */
+-#define EP_W4_MEDIA_TYPE 0x0a
+-#define EP_W4_CTRLR_STATUS 0x08
+-#define EP_W4_NET_DIAG 0x06
+-#define EP_W4_FIFO_DIAG 0x04
+-#define EP_W4_HOST_DIAG 0x02
+-#define EP_W4_TX_DIAG 0x00
+-
+-/*
+- * Window 5 Registers. Results and Internal status.
+- */
+-/* Read */
+-#define EP_W5_READ_0_MASK 0x0c
+-#define EP_W5_INTR_MASK 0x0a
+-#define EP_W5_RX_FILTER 0x08
+-#define EP_W5_RX_EARLY_THRESH 0x06
+-#define EP_W5_TX_AVAIL_THRESH 0x02
+-#define EP_W5_TX_START_THRESH 0x00
+-
+-/*
+- * Window 6 registers. Statistics.
+- */
+-/* Read/Write */
+-#define TX_TOTAL_OK 0x0c
+-#define RX_TOTAL_OK 0x0a
+-#define TX_DEFERRALS 0x08
+-#define RX_FRAMES_OK 0x07
+-#define TX_FRAMES_OK 0x06
+-#define RX_OVERRUNS 0x05
+-#define TX_COLLISIONS 0x04
+-#define TX_AFTER_1_COLLISION 0x03
+-#define TX_AFTER_X_COLLISIONS 0x02
+-#define TX_NO_SQE 0x01
+-#define TX_CD_LOST 0x00
+-
+-/****************************************
+- *
+- * Register definitions.
+- *
+- ****************************************/
+-
+-/*
+- * Command register. All windows.
+- *
+- * 16 bit register.
+- * 15-11: 5-bit code for command to be executed.
+- * 10-0: 11-bit arg if any. For commands with no args;
+- * this can be set to anything.
+- */
+-#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms
+- * after issuing */
+-#define WINDOW_SELECT (unsigned short) (0x1<<11)
+-#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to
+- * determine whether
+- * this is needed. If
+- * so; wait 800 uSec
+- * before using trans-
+- * ceiver. */
+-#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on
+- * power-up */
+-#define RX_ENABLE (unsigned short) (0x4<<11)
+-#define RX_RESET (unsigned short) (0x5<<11)
+-#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11)
+-#define TX_ENABLE (unsigned short) (0x9<<11)
+-#define TX_DISABLE (unsigned short) (0xa<<11)
+-#define TX_RESET (unsigned short) (0xb<<11)
+-#define REQ_INTR (unsigned short) (0xc<<11)
+-#define SET_INTR_MASK (unsigned short) (0xe<<11)
+-#define SET_RD_0_MASK (unsigned short) (0xf<<11)
+-#define SET_RX_FILTER (unsigned short) (0x10<<11)
+-#define FIL_INDIVIDUAL (unsigned short) (0x1)
+-#define FIL_GROUP (unsigned short) (0x2)
+-#define FIL_BRDCST (unsigned short) (0x4)
+-#define FIL_ALL (unsigned short) (0x8)
+-#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11)
+-#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11)
+-#define SET_TX_START_THRESH (unsigned short) (0x13<<11)
+-#define STATS_ENABLE (unsigned short) (0x15<<11)
+-#define STATS_DISABLE (unsigned short) (0x16<<11)
+-#define STOP_TRANSCEIVER (unsigned short) (0x17<<11)
+-/*
+- * The following C_* acknowledge the various interrupts. Some of them don't
+- * do anything. See the manual.
+- */
+-#define ACK_INTR (unsigned short) (0x6800)
+-#define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1)
+-#define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2)
+-#define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4)
+-#define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8)
+-#define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10)
+-#define C_RX_EARLY (unsigned short) (ACK_INTR|0x20)
+-#define C_INT_RQD (unsigned short) (ACK_INTR|0x40)
+-#define C_UPD_STATS (unsigned short) (ACK_INTR|0x80)
+-
+-/*
+- * Status register. All windows.
+- *
+- * 15-13: Window number(0-7).
+- * 12: Command_in_progress.
+- * 11: reserved.
+- * 10: reserved.
+- * 9: reserved.
+- * 8: reserved.
+- * 7: Update Statistics.
+- * 6: Interrupt Requested.
+- * 5: RX Early.
+- * 4: RX Complete.
+- * 3: TX Available.
+- * 2: TX Complete.
+- * 1: Adapter Failure.
+- * 0: Interrupt Latch.
+- */
+-#define S_INTR_LATCH (unsigned short) (0x1)
+-#define S_CARD_FAILURE (unsigned short) (0x2)
+-#define S_TX_COMPLETE (unsigned short) (0x4)
+-#define S_TX_AVAIL (unsigned short) (0x8)
+-#define S_RX_COMPLETE (unsigned short) (0x10)
+-#define S_RX_EARLY (unsigned short) (0x20)
+-#define S_INT_RQD (unsigned short) (0x40)
+-#define S_UPD_STATS (unsigned short) (0x80)
+-#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
+- S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
+-#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000)
+-
+-/*
+- * FIFO Registers.
+- * RX Status. Window 1/Port 08
+- *
+- * 15: Incomplete or FIFO empty.
+- * 14: 1: Error in RX Packet 0: Incomplete or no error.
+- * 13-11: Type of error.
+- * 1000 = Overrun.
+- * 1011 = Run Packet Error.
+- * 1100 = Alignment Error.
+- * 1101 = CRC Error.
+- * 1001 = Oversize Packet Error (>1514 bytes)
+- * 0010 = Dribble Bits.
+- * (all other error codes, no errors.)
+- *
+- * 10-0: RX Bytes (0-1514)
+- */
+-#define ERR_RX_INCOMPLETE (unsigned short) (0x1<<15)
+-#define ERR_RX (unsigned short) (0x1<<14)
+-#define ERR_RX_OVERRUN (unsigned short) (0x8<<11)
+-#define ERR_RX_RUN_PKT (unsigned short) (0xb<<11)
+-#define ERR_RX_ALIGN (unsigned short) (0xc<<11)
+-#define ERR_RX_CRC (unsigned short) (0xd<<11)
+-#define ERR_RX_OVERSIZE (unsigned short) (0x9<<11)
+-#define ERR_RX_DRIBBLE (unsigned short) (0x2<<11)
+-
+-/*
+- * FIFO Registers.
+- * TX Status. Window 1/Port 0B
+- *
+- * Reports the transmit status of a completed transmission. Writing this
+- * register pops the transmit completion stack.
+- *
+- * Window 1/Port 0x0b.
+- *
+- * 7: Complete
+- * 6: Interrupt on successful transmission requested.
+- * 5: Jabber Error (TP Only, TX Reset required. )
+- * 4: Underrun (TX Reset required. )
+- * 3: Maximum Collisions.
+- * 2: TX Status Overflow.
+- * 1-0: Undefined.
+- *
+- */
+-#define TXS_COMPLETE 0x80
+-#define TXS_SUCCES_INTR_REQ 0x40
+-#define TXS_JABBER 0x20
+-#define TXS_UNDERRUN 0x10
+-#define TXS_MAX_COLLISION 0x8
+-#define TXS_STATUS_OVERFLOW 0x4
+-
+-/*
+- * Configuration control register.
+- * Window 0/Port 04
+- */
+-/* Read */
+-#define IS_AUI (1<<13)
+-#define IS_BNC (1<<12)
+-#define IS_UTP (1<<9)
+-/* Write */
+-#define ENABLE_DRQ_IRQ 0x0001
+-#define W0_P4_CMD_RESET_ADAPTER 0x4
+-#define W0_P4_CMD_ENABLE_ADAPTER 0x1
+-/*
+- * Media type and status.
+- * Window 4/Port 0A
+- */
+-#define ENABLE_UTP 0xc0
+-#define DISABLE_UTP 0x0
+-
+-/*
+- * Resource control register
+- */
+-
+-#define SET_IRQ(i) ( ((i)<<12) | 0xF00) /* set IRQ i */
+-
+-/*
+- * Receive status register
+- */
+-
+-#define RX_BYTES_MASK (unsigned short) (0x07ff)
+-#define RX_ERROR 0x4000
+-#define RX_INCOMPLETE 0x8000
+-
+-
+-/*
+- * Misc defines for various things.
+- */
+-#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
+-#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
+-#define PROD_ID 0x9150
+-
+-#define AUI 0x1
+-#define BNC 0x2
+-#define UTP 0x4
+-
+-#define RX_BYTES_MASK (unsigned short) (0x07ff)
+-
+- /* EISA support */
+-#define EP_EISA_START 0x1000
+-#define EP_EISA_W0 0x0c80
+-
+-#ifdef INCLUDE_3C529
+- /* MCA support */
+-#define MCA_MOTHERBOARD_SETUP_REG 0x94
+-#define MCA_ADAPTER_SETUP_REG 0x96
+-#define MCA_MAX_SLOT_NR 8
+-#define MCA_POS_REG(n) (0x100+(n))
+-#endif
+-
+-/*
+- * Local variables:
+- * c-basic-offset: 8
+- * End:
+- */
+diff -Naur grub-0.97.orig/netboot/3c595.c grub-0.97/netboot/3c595.c
+--- grub-0.97.orig/netboot/3c595.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/3c595.c 2005-08-31 19:03:35.000000000 +0000
+@@ -20,6 +20,7 @@
+ *
+ * Copyright (c) 1994 Herb Peyerl <hpeyerl@novatel.ca>
+ *
++* timlegge 08-24-2003 Add Multicast Support
+ */
+
+ /* #define EDEBUG */
+@@ -30,7 +31,7 @@
+ #include "3c595.h"
+ #include "timer.h"
+
+-static unsigned short eth_nic_base, eth_asic_base;
++static unsigned short eth_nic_base;
+ static unsigned short vx_connector, vx_connectors;
+
+ static struct connector_entry {
+@@ -57,14 +58,12 @@
+ static void vxgetlink(void);
+ static void vxsetlink(void);
+
+-#define udelay(n) waiton_timer2(((n)*TICKS_PER_MS)/1000)
+-
+ /**************************************************************************
+ ETH_RESET - Reset adapter
+ ***************************************************************************/
+ static void t595_reset(struct nic *nic)
+ {
+- int i, j;
++ int i;
+
+ /***********************************************************
+ Reset 3Com 595 card
+@@ -133,7 +132,7 @@
+ outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
+
+ outw(SET_RX_FILTER | FIL_INDIVIDUAL |
+- FIL_BRDCST, BASE + VX_COMMAND);
++ FIL_BRDCST|FIL_MULTICAST, BASE + VX_COMMAND);
+
+ vxsetlink();
+ /*{
+@@ -225,10 +224,9 @@
+ /**************************************************************************
+ ETH_POLL - Wait for a frame
+ ***************************************************************************/
+-static int t595_poll(struct nic *nic)
++static int t595_poll(struct nic *nic, int retrieve)
+ {
+ /* common variables */
+- unsigned short type = 0; /* used by EDEBUG */
+ /* variables for 3C595 */
+ short status, cst;
+ register short rx_fifo;
+@@ -262,6 +260,8 @@
+ if (rx_fifo==0)
+ return 0;
+
++ if ( ! retrieve ) return 1;
++
+ /* read packet */
+ #ifdef EDEBUG
+ printf("[l=%d",rx_fifo);
+@@ -300,12 +300,15 @@
+ outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
+ while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS);
+ #ifdef EDEBUG
++{
++ unsigned short type = 0; /* used by EDEBUG */
+ type = (nic->packet[12]<<8) | nic->packet[13];
+ if(nic->packet[0]+nic->packet[1]+nic->packet[2]+nic->packet[3]+nic->packet[4]+
+ nic->packet[5] == 0xFF*ETH_ALEN)
+ printf(",t=%hX,b]",type);
+ else
+ printf(",t=%hX]",type);
++}
+ #endif
+ return 1;
+ }
+@@ -382,9 +385,8 @@
+ static void
+ vxsetlink(void)
+ {
+- int i, j, k;
++ int i, j;
+ char *reason, *warning;
+- static short prev_flags;
+ static char prev_conn = -1;
+
+ if (prev_conn == -1) {
+@@ -438,28 +440,47 @@
+ GO_WINDOW(1);
+ }
+
+-static void t595_disable(struct nic *nic)
++static void t595_disable(struct dev *dev)
+ {
+- outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
+- udelay(8000);
+- GO_WINDOW(4);
+- outw(0, BASE + VX_W4_MEDIA_TYPE);
+- GO_WINDOW(1);
++ struct nic *nic = (struct nic *)dev;
++ t595_reset(nic);
++
++ outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
++ udelay(8000);
++ GO_WINDOW(4);
++ outw(0, BASE + VX_W4_MEDIA_TYPE);
++ GO_WINDOW(1);
++}
++
++static void t595_irq(struct nic *nic __unused, irq_action_t action __unused)
++{
++ switch ( action ) {
++ case DISABLE :
++ break;
++ case ENABLE :
++ break;
++ case FORCE :
++ break;
++ }
+ }
+
+ /**************************************************************************
+ ETH_PROBE - Look for an adapter
+ ***************************************************************************/
+-struct nic *t595_probe(struct nic *nic, unsigned short *probeaddrs, struct pci_device *pci)
++static int t595_probe(struct dev *dev, struct pci_device *pci)
+ {
++ struct nic *nic = (struct nic *)dev;
+ int i;
+ unsigned short *p;
+
+- if (probeaddrs == 0 || probeaddrs[0] == 0)
++ if (pci->ioaddr == 0)
+ return 0;
+ /* eth_nic_base = probeaddrs[0] & ~3; */
+ eth_nic_base = pci->ioaddr;
+
++ nic->irqno = 0;
++ nic->ioaddr = pci->ioaddr & ~3;
++
+ GO_WINDOW(0);
+ outw(GLOBAL_RESET, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+@@ -487,14 +508,40 @@
+ printf("Ethernet address: %!\n", nic->node_addr);
+
+ t595_reset(nic);
+- nic->reset = t595_reset;
+- nic->poll = t595_poll;
++ dev->disable = t595_disable;
++ nic->poll = t595_poll;
+ nic->transmit = t595_transmit;
+- nic->disable = t595_disable;
+- return nic;
++ nic->irq = t595_irq;
++ return 1;
+
+ }
+
++static struct pci_id t595_nics[] = {
++PCI_ROM(0x10b7, 0x5900, "3c590", "3Com590"), /* Vortex 10Mbps */
++PCI_ROM(0x10b7, 0x5950, "3c595", "3Com595"), /* Vortex 100baseTx */
++PCI_ROM(0x10b7, 0x5951, "3c595-1", "3Com595"), /* Vortex 100baseT4 */
++PCI_ROM(0x10b7, 0x5952, "3c595-2", "3Com595"), /* Vortex 100base-MII */
++PCI_ROM(0x10b7, 0x9000, "3c900-tpo", "3Com900-TPO"), /* 10 Base TPO */
++PCI_ROM(0x10b7, 0x9001, "3c900-t4", "3Com900-Combo"), /* 10/100 T4 */
++PCI_ROM(0x10b7, 0x9004, "3c900b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
++PCI_ROM(0x10b7, 0x9005, "3c900b-combo", "3Com900B-Combo"), /* 10 Base Combo */
++PCI_ROM(0x10b7, 0x9006, "3c900b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
++PCI_ROM(0x10b7, 0x900a, "3c900b-fl", "3Com900B-FL"), /* 10 Base F */
++PCI_ROM(0x10b7, 0x9800, "3c980-cyclone-1", "3Com980-Cyclone"), /* Cyclone */
++PCI_ROM(0x10b7, 0x9805, "3c9805-1", "3Com9805"), /* Dual Port Server Cyclone */
++PCI_ROM(0x10b7, 0x7646, "3csoho100-tx-1", "3CSOHO100-TX"), /* Hurricane */
++PCI_ROM(0x10b7, 0x4500, "3c450-1", "3Com450 HomePNA Tornado"),
++};
++
++struct pci_driver t595_driver = {
++ .type = NIC_DRIVER,
++ .name = "3C595",
++ .probe = t595_probe,
++ .ids = t595_nics,
++ .id_count = sizeof(t595_nics)/sizeof(t595_nics[0]),
++ .class = 0,
++};
++
+ /*
+ * Local variables:
+ * c-basic-offset: 8
+diff -Naur grub-0.97.orig/netboot/3c90x.c grub-0.97/netboot/3c90x.c
+--- grub-0.97.orig/netboot/3c90x.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/3c90x.c 2005-08-31 19:03:35.000000000 +0000
+@@ -1,7 +1,7 @@
+ /*
+ * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
+ * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
+- * Steve.Smith@Juno.Com
++ * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
+ *
+ * This program Copyright (C) 1999 LightSys Technology Services, Inc.
+ * Portions Copyright (C) 1999 Steve Smith
+@@ -31,13 +31,15 @@
+ * Re-wrote poll and transmit for
+ * better error recovery and heavy
+ * network traffic operation
++ * v2.01 5-26-2003 NN Fixed driver alignment issue which
++ * caused system lockups if driver structures
++ * not 8-byte aligned.
+ *
+ */
+
+ #include "etherboot.h"
+ #include "nic.h"
+ #include "pci.h"
+-#include "cards.h"
+ #include "timer.h"
+
+ #define XCVR_MAGIC (0x5A00)
+@@ -47,9 +49,6 @@
+ **/
+ #define XMIT_RETRIES 250
+
+-#undef virt_to_bus
+-#define virt_to_bus(x) ((unsigned long)x)
+-
+ /*** Register definitions for the 3c905 ***/
+ enum Registers
+ {
+@@ -225,7 +224,7 @@
+ unsigned int DataAddr;
+ unsigned int DataLength;
+ }
+- TXD;
++ TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
+
+ /*** RX descriptor ***/
+ typedef struct
+@@ -235,7 +234,7 @@
+ unsigned int DataAddr;
+ unsigned int DataLength;
+ }
+- RXD;
++ RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
+
+ /*** Global variables ***/
+ static struct
+@@ -311,6 +310,7 @@
+ }
+
+
++#if 0
+ /*** a3c90x_internal_WriteEepromWord - write a physical word of
+ *** data to the onboard serial eeprom (not the BIOS prom, but the
+ *** nvram in the card that stores, among other things, the MAC
+@@ -344,8 +344,9 @@
+
+ return 0;
+ }
++#endif
+
+-
++#if 0
+ /*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
+ *** and re-compute the eeprom checksum.
+ ***/
+@@ -384,8 +385,7 @@
+
+ return 0;
+ }
+-
+-
++#endif
+
+ /*** a3c90x_reset: exported function that resets the card to its default
+ *** state. This is so the Linux driver can re-set the card up the way
+@@ -393,12 +393,10 @@
+ *** not alter the selected transceiver that we used to download the boot
+ *** image.
+ ***/
+-static void
+-a3c90x_reset(struct nic *nic)
++static void a3c90x_reset(void)
+ {
+- int cfg;
+-
+ #ifdef CFG_3C90X_PRESERVE_XCVR
++ int cfg;
+ /** Read the current InternalConfig value. **/
+ a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
+ cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
+@@ -473,7 +471,7 @@
+ *** p - the pointer to the packet data itself.
+ ***/
+ static void
+-a3c90x_transmit(struct nic *nic, const char *d, unsigned int t,
++a3c90x_transmit(struct nic *nic __unused, const char *d, unsigned int t,
+ unsigned int s, const char *p)
+ {
+
+@@ -553,7 +551,7 @@
+ if (status & 0x02)
+ {
+ printf("3C90X: Tx Reclaim Error (%hhX)\n", status);
+- a3c90x_reset(NULL);
++ a3c90x_reset();
+ }
+ else if (status & 0x04)
+ {
+@@ -572,18 +570,18 @@
+ else if (status & 0x10)
+ {
+ printf("3C90X: Tx Underrun (%hhX)\n", status);
+- a3c90x_reset(NULL);
++ a3c90x_reset();
+ }
+ else if (status & 0x20)
+ {
+ printf("3C90X: Tx Jabber (%hhX)\n", status);
+- a3c90x_reset(NULL);
++ a3c90x_reset();
+ }
+ else if ((status & 0x80) != 0x80)
+ {
+ printf("3C90X: Internal Error - Incomplete Transmission (%hhX)\n",
+ status);
+- a3c90x_reset(NULL);
++ a3c90x_reset();
+ }
+ }
+
+@@ -601,7 +599,7 @@
+ *** in nic->packetlen. Return 1 if a packet was found.
+ ***/
+ static int
+-a3c90x_poll(struct nic *nic)
++a3c90x_poll(struct nic *nic, int retrieve)
+ {
+ int i, errcode;
+
+@@ -610,6 +608,8 @@
+ return 0;
+ }
+
++ if ( ! retrieve ) return 1;
++
+ /** we don't need to acknowledge rxComplete -- the upload engine
+ ** does it for us.
+ **/
+@@ -663,34 +663,51 @@
+ *** [Ken]
+ ***/
+ static void
+-a3c90x_disable(struct nic *nic)
+- {
++a3c90x_disable(struct dev *dev __unused)
++{
++ /* reset and disable merge */
++ a3c90x_reset();
+ /* Disable the receiver and transmitter. */
+ outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
+ outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
+- }
+-
++}
+
++static void a3c90x_irq(struct nic *nic __unused, irq_action_t action __unused)
++{
++ switch ( action ) {
++ case DISABLE :
++ break;
++ case ENABLE :
++ break;
++ case FORCE :
++ break;
++ }
++}
+
+ /*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
+ *** initialization. If this routine is called, the pci functions did find the
+ *** card. We just have to init it here.
+ ***/
+-struct nic*
+-a3c90x_probe(struct nic *nic, unsigned short *probeaddrs, struct pci_device *pci)
+- {
++static int a3c90x_probe(struct dev *dev, struct pci_device *pci)
++{
++ struct nic *nic = (struct nic *)dev;
+ int i, c;
+ unsigned short eeprom[0x21];
+ unsigned int cfg;
+ unsigned int mopt;
++ unsigned int mstat;
+ unsigned short linktype;
++#define HWADDR_OFFSET 10
+
+- if (probeaddrs == 0 || probeaddrs[0] == 0)
++ if (pci->ioaddr == 0)
+ return 0;
+
+ adjust_pci_device(pci);
+
+- INF_3C90X.IOAddr = probeaddrs[0] & ~3;
++ nic->ioaddr = pci->ioaddr & ~3;
++ nic->irqno = 0;
++
++ INF_3C90X.IOAddr = pci->ioaddr & ~3;
+ INF_3C90X.CurrentWindow = 255;
+ switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
+ {
+@@ -756,30 +773,45 @@
+ "Copyright 1999 LightSys Technology Services, Inc.\n"
+ "Portions Copyright 1999 Steve Smith\n");
+ printf("Provided with ABSOLUTELY NO WARRANTY.\n");
++#ifdef CFG_3C90X_BOOTROM_FIX
++ if (INF_3C90X.isBrev)
++ {
++ printf("NOTE: 3c905b bootrom fix enabled; has side "
++ "effects. See 3c90x.txt for info.\n");
++ }
++#endif
+ printf("-------------------------------------------------------"
+ "------------------------\n");
+
+ /** Retrieve the Hardware address and print it on the screen. **/
+- INF_3C90X.HWAddr[0] = eeprom[0]>>8;
+- INF_3C90X.HWAddr[1] = eeprom[0]&0xFF;
+- INF_3C90X.HWAddr[2] = eeprom[1]>>8;
+- INF_3C90X.HWAddr[3] = eeprom[1]&0xFF;
+- INF_3C90X.HWAddr[4] = eeprom[2]>>8;
+- INF_3C90X.HWAddr[5] = eeprom[2]&0xFF;
++ INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
++ INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
++ INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
++ INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
++ INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
++ INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
+ printf("MAC Address = %!\n", INF_3C90X.HWAddr);
+
++ /* Test if the link is good, if not continue */
++ a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winDiagnostics4);
++ mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
++ if((mstat & (1<<11)) == 0) {
++ printf("Valid link not established\n");
++ return 0;
++ }
++
+ /** Program the MAC address into the station address registers **/
+ a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
+- outw(htons(eeprom[0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
+- outw(htons(eeprom[1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
+- outw(htons(eeprom[2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
++ outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
++ outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
++ outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
+ outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
+ outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
+ outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
+
+ /** Fill in our entry in the etherboot arp table **/
+ for(i=0;i<ETH_ALEN;i++)
+- nic->node_addr[i] = (eeprom[i/2] >> (8*((i&1)^1))) & 0xff;
++ nic->node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
+
+ /** Read the media options register, print a message and set default
+ ** xcvr.
+@@ -903,8 +935,8 @@
+ while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
+ ;
+
+- /** Set the RX filter = receive only individual pkts & bcast. **/
+- a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x04);
++ /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
++ a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
+ a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
+
+
+@@ -918,12 +950,46 @@
+ cmdAcknowledgeInterrupt, 0x661);
+
+ /** Set our exported functions **/
+- nic->reset = a3c90x_reset;
++ dev->disable = a3c90x_disable;
+ nic->poll = a3c90x_poll;
+ nic->transmit = a3c90x_transmit;
+- nic->disable = a3c90x_disable;
++ nic->irq = a3c90x_irq;
+
+- return nic;
+- }
++ return 1;
++}
+
+
++static struct pci_id a3c90x_nics[] = {
++/* Original 90x revisions: */
++PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
++PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
++PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
++PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
++/* Newer 90xB revisions: */
++PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
++PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
++PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
++PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
++PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
++PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
++PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
++PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
++/* Newer 90xC revision: */
++PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
++PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
++PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
++PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
++PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
++PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
++PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
++PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
++};
++
++struct pci_driver a3c90x_driver = {
++ .type = NIC_DRIVER,
++ .name = "3C90X",
++ .probe = a3c90x_probe,
++ .ids = a3c90x_nics,
++ .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
++ .class = 0,
++};
+diff -Naur grub-0.97.orig/netboot/3c90x.txt grub-0.97/netboot/3c90x.txt
+--- grub-0.97.orig/netboot/3c90x.txt 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/3c90x.txt 1970-01-01 00:00:00.000000000 +0000
+@@ -1,307 +0,0 @@
+-
+- Instructions for use of the 3C90X driver for EtherBoot
+-
+- Original 3C905B support by:
+- Greg Beeley (Greg.Beeley@LightSys.org),
+- LightSys Technology Services, Inc.
+- February 11, 1999
+-
+- Updates for 3C90X family by:
+- Steve Smith (steve.smith@juno.com)
+- October 1, 1999
+-
+- Minor documentation updates by
+- Greg Beeley (Greg.Beeley@LightSys.org)
+- March 29, 2000
+-
+--------------------------------------------------------------------------------
+-
+-I OVERVIEW
+-
+- The 3c90X series ethernet cards are a group of high-performance busmaster
+- DMA cards from 3Com. This particular driver supports both the 3c90x and
+- the 3c90xB revision cards. 3C90xC family support has been tested to some
+- degree but not extensively.
+-
+- Here's the licensing information:
+-
+- This program Copyright (C) 1999 LightSys Technology Services, Inc.
+- Portions Copyright (C) 1999 Steve Smith.
+-
+- This program may be re-distributed in source or binary form, modified,
+- sold, or copied for any purpose, provided that the above copyright message
+- and this text are included with all source copies or derivative works, and
+- provided that the above copyright message and this text are included in the
+- documentation of any binary-only distributions. This program is
+- distributed WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR
+- A PARTICULAR PURPOSE or MERCHANTABILITY. Please read the associated
+- documentation "3c90x.txt" before compiling and using this driver.
+-
+-
+-II FLASH PROMS
+-
+- The 3c90xB cards, according to the 3Com documentation, only accept the
+- following flash memory chips:
+-
+- Atmel AT29C512 (64 kilobyte)
+- Atmel AT29C010 (128 kilobyte)
+-
+- The 3c90x cards, according to the 3Com documentation, accept the
+- following flash memory chips capacities:
+-
+- 64 kb (8 kB)
+- 128 kb (16 kB)
+- 256 kb (32 kB) and
+- 512 kb (64 kB)
+-
+- Atmel AT29C512 (64 kilobyte) chips are specifically listed for both
+- adapters, but flashing on the 3c905b cards would only be supported
+- through the Atmel parts. Any device, of the supported size, should
+- be supported when programmed by a dedicated PROM programmer (e.g.
+- not the card).
+-
+- To use this driver in such a PROM, visit Atmel's web site and download
+- their .PDF file containing a list of their distributors. Contact the
+- distributors for pricing information. The prices are quite reasonable
+- (about $3 US each for the 64 kB part), and are comparable to what one would
+- expect for similarly sized standard EPROMs. And, the flash chips are much
+- easier to work with, as they don't need to be UV-erased to be reprogrammed.
+- The 3C905B card actually provides a method to program the flash memory
+- while it is resident on board the card itself; if someone would like to
+- write a small DOS program to do the programming, I can provide the
+- information about the registers and so forth.
+-
+- A utility program, 3c90xutil, is provided with Etherboot in the 'contrib'
+- directory that allows for the on-board flashing of the ROM while Linux
+- is running. The program has been successfully used under Linux, but I
+- have heard problem reports of its use under FreeBSD. Anyone willing to
+- make it work under FreeBSD is more than welcome to do so!
+-
+- You also have the option of using EPROM chips - the 3C905B-TX-NM has been
+- successfully tested with 27C256 (32kB) and 27C512 (64kB) chips with a
+- specified access time of 100ns and faster.
+-
+-
+-III GENERAL USE
+-
+- Normally, the basic procedure for using this driver is as follows:
+-
+- 1. Run the 3c90xcfg program on the driver diskette to enable the
+- boot PROM and set it to 64k or 128k, as appropriate.
+- 2. Build the appropriate 3c90x.fd0 or 3c90x.fd0 floppy image with
+- possibly the value CFG_3C90X_XCVR defined to the transceiver type that
+- you want to use (i.e., 10/100 rj45, AUI, coax, MII).
+- 3. Run the floppy image on the PC to be network booted, to get
+- it configured, and to verify that it will boot properly.
+- 4. Build the 3c90x.rom or 3c90x.lzrom PROM image and program
+- it into the flash or EPROM memory chip.
+- 5. Put the PROM in the ethernet card, boot and enable 'boot from
+- network first' in the system BIOS, save and reboot.
+-
+- Here are some issues to be aware of:
+-
+- 1. If you experience crashes or different behaviour when using the
+- boot PROM, add the setting CFG_3C90X_BOOTROM_FIX and go through the
+- steps 2-5 above. This works around a bug in some 3c905B cards (see
+- below), but has some side-effects which may not be desirable.
+- Please note that you have to boot off a floppy (not PROM!) once for
+- this fix to take effect.
+- 2. The possible need to manually set the CFG_3C90X_XCVR value to
+- configure the transceiver type. Values are listed below.
+- 3. The possible need to define CFG_3C90X_PRESERVE_XCVR for use in
+- operating systems that don't intelligently determine the
+- transceiver type.
+-
+- Some things that are on the 'To-Do' list, perhaps for me, but perhaps
+- for any other volunteers out there:
+-
+- 1. Extend the driver to fully implement the auto-select
+- algorithm if the card has multiple media ports.
+- 2. Fix any bugs in the code <grin>....
+- 3. Extend the driver to support the 3c905c revision cards
+- "officially". Right now, the support has been primarily empirical
+- and not based on 3c905C documentation.
+-
+- Now for the details....
+-
+- This driver has been tested on roughly 300 systems. The main two
+- configuration issues to contend with are:
+-
+- 1. Ensure that PCI Busmastering is enabled for the adapter (configured
+- in the CMOS setup)
+- 2. Some systems don't work properly with the adapter when plug and
+- play OS is enabled; I always set it to "No" or "Disabled" -- this makes
+- it easier and really doesn't adversely affect anything.
+-
+- Roughly 95% of the systems worked when configured properly. A few
+- have issues with booting locally once the boot PROM has been installed
+- (this number has been less than 2%). Other configuration issues that
+- to check:
+-
+- 1. Newer BIOS's actually work correctly with the network boot order.
+- Set the network adapter first. Most older BIOS's automatically go to
+- the network boot PROM first.
+- 2. For systems where the adapter was already installed and is just
+- having the PROM installed, try setting the "reset configuration data"
+- to yes in the CMOS setup if the BIOS isn't seen at first. If your BIOS
+- doesn't have this option, remove the card, start the system, shut down,
+- install the card and restart (or switch to a different PCI slot).
+- 3. Make sure the CMOS security settings aren't preventing a boot.
+-
+- The 3c905B cards have a significant 'bug' that relates to the flash prom:
+- unless the card is set internally to the MII transceiver, it will only
+- read the first 8k of the PROM image. Don't ask why -- it seems really
+- obscure, but it has to do with the way they mux'd the address lines
+- from the PCI bus to the ROM. Unfortunately, most of us are not using
+- MII transceivers, and even the .lzrom image ends up being just a little
+- bit larger than 8k. Note that the workaround for this is disabled by
+- default, because the Windows NT 4.0 driver does not like it (no packets
+- are transmitted).
+-
+- So, the solution that I've used is to internally set the card's nvram
+- configuration to use MII when it boots. The 3c905b driver does this
+- automatically. This way, the 16k prom image can be loaded into memory,
+- and then the 3c905b driver can set the temporary configuration of the
+- card to an appropriate value, either configurable by the user or chosen
+- by the driver.
+-
+- To enable the 3c905B bugfix, which is necessary for these cards when
+- booting from the Flash ROM, define -DCFG_3C90X_BOOTROM_FIX when building,
+- create a floppy image and boot it once.
+- Thereafter, the card should accept the larger prom image.
+-
+- The driver should choose an appropriate transceiver on the card. However,
+- if it doesn't on your card or if you need to, for instance, set your
+- card to 10mbps when connected to an unmanaged 10/100 hub, you can specify
+- which transceiver you want to use. To do this, build the 3c905b.fd0
+- image with -DCFG_3C90X_XCVR=x, where 'x' is one of the following
+- values:
+-
+- 0 10Base-T
+- 1 10mbps AUI
+- 3 10Base-2 (thinnet/coax)
+- 4 100Base-TX
+- 5 100Base-FX
+- 6 MII
+- 8 Auto-negotiation 10Base-T / 100Base-TX (usually the default)
+- 9 MII External MAC Mode
+- 255 Allow driver to choose an 'appropriate' media port.
+-
+- Then proceed from step 2 in the above 'general use' instructions. The
+- .rom image can be built with CFG_3C90X_XCVR set to a value, but you
+- normally don't want to do this, since it is easier to change the
+- transceiver type by rebuilding a new floppy, changing the BIOS to floppy
+- boot, booting, and then changing the BIOS back to network boot. If
+- CFG_3C90X_XCVR is not set in a particular build, it just uses the
+- current configuration (either its 'best guess' or whatever the stored
+- CFG_3C90X_XCVR value was from the last time it was set).
+-
+- [[ Note for the more technically inclined: The CFG_3C90X_XCVR value is
+- programmed into a register in the card's NVRAM that was reserved for
+- LanWorks PROM images to use. When the driver boots, the card comes
+- up in MII mode, and the driver checks the LanWorks register to find
+- out if the user specified a transceiver type. If it finds that
+- information, it uses that, otherwise it picks a transceiver that the
+- card has based on the 3c905b's MediaOptions register. This driver isn't
+- quite smart enough to always determine which media port is actually
+- _connected_; maybe someone else would like to take on that task (it
+- actually involves sending a self-directed packet and seeing if it
+- comes back. IF it does, that port is connected). ]]
+-
+- Another issue to keep in mind is that it is possible that some OS'es
+- might not be happy with the way I've handled the PROM-image hack with
+- setting MII mode on bootup. Linux 2.0.35 does not have this problem.
+- Behavior of other systems may vary. The 3com documentation specifically
+- says that, at least with the card that I have, the device driver in the
+- OS should auto-select the media port, so other drivers should work fine
+- with this 'hack'. However, if yours doesn't seem to, you can try defining
+- CFG_3C90X_PRESERVE_XCVR when building to cause Etherboot to keep the
+- working setting (that allowed the bootp/tftp process) across the eth_reset
+- operation.
+-
+-
+-IV FOR DEVELOPERS....
+-
+- If you would like to fix/extend/etc. this driver, feel free to do so; just
+- be sure you can test the modified version on the 3c905B-TX cards that the
+- driver was originally designed for. This section of this document gives
+- some information that might be relevant to a programmer.
+-
+- A. Main Entry Point
+-
+- a3c90x_probe is the main entry point for this driver. It is referred
+- to in an array in 'config.c'.
+-
+- B. Other Important Functions
+-
+- The functions a3c90x_transmit, a3c90x_poll, a3c90x_reset, and
+- a3c90x_disable are static functions that EtherBoot finds out about
+- as a result of a3c90x_probe setting entries in the nic structure
+- for them. The EtherBoot framework does not use interrupts. It is
+- polled. All transmit and receive operations are initiated by the
+- etherboot framework, not by an interrupt or by the driver.
+-
+- C. Internal Functions
+-
+- The following functions are internal to the driver:
+-
+- a3c90x_internal_IssueCommand - sends a command to the 3c905b card.
+- a3c90x_internal_SetWindow - shifts between one of eight register
+- windows onboard the 3c90x. The bottom 16 bytes of the card's
+- I/O space are multiplexed among 128 bytes, only 16 of which are
+- visible at any one time. This SetWindow function selects one of
+- the eight sets.
+- a3c90x_internal_ReadEeprom - reads a word (16 bits) from the
+- card's onboard nvram. This is NOT the BIOS boot rom. This is
+- where the card stores such things as its hardware address.
+- a3c90x_internal_WriteEeprom - writes a word (16 bits) to the
+- card's nvram, and recomputes the eeprom checksum.
+- a3c90x_internal_WriteEepromWord - writes a word (16 bits) to the
+- card's nvram. Used by the above routine.
+- a3c90x_internal_WriteEepromWord - writes a word (16 bits) to the
+- card's nvram. Used by the above routine.
+-
+- D. Globals
+-
+- All global variables are inside a global structure named INF_3C90X.
+- So, wherever you see that structure referenced, you know the variable
+- is a global. Just keeps things a little neater.
+-
+- E. Enumerations
+-
+- There are quite a few enumerated type definitions for registers and
+- so forth, many for registers that I didn't even touch in the driver.
+- Register types start with 'reg', window numbers (for SetWindow)
+- start with 'win', and commands (for IssueCommand) start with 'cmd'.
+- Register offsets also include an indication in the name as to the
+- size of the register (_b = byte, _w = word, _l = long), and which
+- window the register is in, if it is windowed (0-7).
+-
+- F. Why the 'a3c90x' name?
+-
+- I had to come up with a letter at the beginning of all of the
+- identifiers, since 3com so conveniently had their name start with a
+- number. Another driver used 't' (for 'three'?); I chose 'a' for
+- no reason at all.
+-
+-Addendum by Jorge L. deLyra <delyra@latt.if.usp.br>, 22Nov2000 re
+-working around the 3C905 hardware bug mentioned above:
+-
+-Use this floppy to fix any 3COM model 3C905B PCI 10/100 Ethernet cards
+-that fail to load and run the boot program the first time around. If
+-they have a "Lucent" rather than a "Broadcom" chipset these cards have
+-a configuration bug that causes a hang when trying to load the boot
+-program from the PROM, if you try to use them right out of the box.
+-
+-The boot program in this floppy is the file named 3c905b-tpo100.rom
+-from Etherboot version 4.6.10, compiled with the bugfix parameter
+-
+- CFG_3C90X_BOOTROM_FIX
+-
+-You have to take the chip off the card and boot the system once using
+-this floppy. Once loaded from the floppy, the boot program will access
+-the card and change some setting in it, correcting the problem. After
+-that you may use either this boot program or the normal one, compiled
+-without this bugfix parameter, to boot the machine from the PROM chip.
+-
+-[Any recent Etherboot version should do, not just 4.6.10 - Ed.]
+diff -Naur grub-0.97.orig/netboot/Makefile.am grub-0.97/netboot/Makefile.am
+--- grub-0.97.orig/netboot/Makefile.am 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/Makefile.am 2005-08-31 19:03:35.000000000 +0000
+@@ -10,58 +10,72 @@
+
+ noinst_LIBRARIES = $(LIBDRIVERS)
+
+-libdrivers_a_SOURCES = cards.h config.c etherboot.h \
+- fsys_tftp.c linux-asm-io.h linux-asm-string.h \
+- main.c misc.c nic.h osdep.h pci.c pci.h timer.c timer.h
+-EXTRA_libdrivers_a_SOURCES = 3c509.c 3c509.h 3c595.c 3c595.h 3c90x.c \
+- cs89x0.c cs89x0.h davicom.c depca.c eepro.c eepro100.c \
+- epic100.c epic100.h fa311.c i82586.c lance.c natsemi.c \
+- ni5010.c ns8390.c ns8390.h otulip.c otulip.h rtl8139.c \
+- sis900.c sis900.h sk_g16.c sk_g16.h smc9000.c smc9000.h \
+- tiara.c tlan.c tulip.c via-rhine.c w89c840.c
++libdrivers_a_SOURCES = big_bswap.h bootp.h byteswap.h config.c cpu.h \
++ dev.h elf.h endian.h etherboot.h fsys_tftp.c grub.h \
++ i386_byteswap.h i386_elf.h i386_endian.h i386_timer.c \
++ if_arp.h if_ether.h igmp.h in.h io.h ip.h isa.h latch.h \
++ little_bswap.h misc.c nic.c nic.h osdep.h pci.c pci.h \
++ pci_ids.h pci_io.c stdint.h tftp.h timer.c timer.h \
++ types.h udp.h mii.h pic8259.c pic8259.h pxe.h basemem.c segoff.h
++EXTRA_libdrivers_a_SOURCES = 3c595.c 3c595.h 3c90x.c davicom.c \
++ e1000.c e1000_hw.h eepro100.c epic100.c epic100.h natsemi.c \
++ ns8390.c ns8390.h pcnet32.c rtl8139.c sis900.c sis900.h \
++ sundance.c tg3.c tg3.h tlan.c tlan.h tulip.c via-rhine.c \
++ w89c840.c r8169.c forcedeth.c ns83820.c pnic.c pnic_api.c \
++ undi.c undi.h
+ libdrivers_a_CFLAGS = $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ -DFSYS_TFTP=1 $(NET_CFLAGS) $(NET_EXTRAFLAGS)
+ # Filled by configure.
+ libdrivers_a_LIBADD = @NETBOOT_DRIVERS@
+ libdrivers_a_DEPENDENCIES = $(libdrivers_a_LIBADD)
+
+-EXTRA_DIST = README.netboot 3c90x.txt cs89x0.txt sis900.txt tulip.txt
++EXTRA_DIST = README.netboot
+
+ # These below are several special rules for the device drivers.
+ # We cannot use a simple rule for them...
+
+ # What objects are derived from a driver?
+-3c509_drivers = 3c509.o 3c529.o
++#3c509_drivers = 3c509.o 3c529.o
+ 3c595_drivers = 3c595.o
+ 3c90x_drivers = 3c90x.o
+-cs89x0_drivers = cs89x0.o
++#cs89x0_drivers = cs89x0.o
+ davicom_drivers = davicom.o
+-depca_drivers = depca.o
+-eepro_drivers = eepro.o
++#depca_drivers = depca.o
++#eepro_drivers = eepro.o
++e1000_drivers = e1000.o
+ eepro100_drivers = eepro100.o
+ epic100_drivers = epic100.o
+ #fa311_drivers = fa311.o
+-i82586_drivers = 3c507.o exos205.o ni5210.o
+-lance_drivers = lance.o ne2100.o ni6510.o
++forcedeth_drivers = forcedeth.o
++#i82586_drivers = 3c507.o exos205.o ni5210.o
++#lance_drivers = lance.o ne2100.o ni6510.o
+ natsemi_drivers = natsemi.o
+-ni5010_drivers = ni5010.o
++#ni5010_drivers = ni5010.o
++ns83820_drivers = ns83820.o
+ ns8390_drivers = 3c503.o ne.o ns8390.o wd.o
+-otulip_drivers = otulip.o
++#otulip_drivers = otulip.o
++pcnet32_drivers = pcnet32.o
++pnic_drivers = pnic.o
++r8169_drivers = r8169.o
+ rtl8139_drivers = rtl8139.o
+ sis900_drivers = sis900.o
+-sk_g16_drivers = sk_g16.o
+-smc9000_drivers = smc9000.o
+-tiara_drivers = tiara.o
+-#tlan_drivers = tlan.o
++#sk_g16_drivers = sk_g16.o
++sundance_driver = sundance.o
++#smc9000_drivers = smc9000.o
++tg3_drivers = tg3.o
++#tiara_drivers = tiara.o
++tlan_drivers = tlan.o
+ tulip_drivers = tulip.o
++undi_drivers = undi.o
+ via_rhine_drivers = via_rhine.o
+ w89c840_drivers = w89c840.o
+
++
+ # Is it really necessary to specify dependecies explicitly?
+-$(3c509_drivers): 3c509.c 3c509.h
+-$(3c509_drivers): %.o: 3c509.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(3c509_drivers): 3c509.c 3c509.h
++#$(3c509_drivers): %.o: 3c509.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+ $(3c595_drivers): 3c595.c 3c595.h
+ $(3c595_drivers): %.o: 3c595.c
+@@ -73,23 +87,28 @@
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(cs89x0_drivers): cs89x0.c cs89x0.h
+-$(cs89x0_drivers): %.o: cs89x0.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(cs89x0_drivers): cs89x0.c cs89x0.h
++#$(cs89x0_drivers): %.o: cs89x0.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+ $(davicom_drivers): davicom.c
+ $(davicom_drivers): %.o: davicom.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(depca_drivers): depca.c
+-$(depca_drivers): %.o: depca.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(depca_drivers): depca.c
++#$(depca_drivers): %.o: depca.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++#$(eepro_drivers): eepro.c
++#$(eepro_drivers): %.o: eepro.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(eepro_drivers): eepro.c
+-$(eepro_drivers): %.o: eepro.c
++$(e1000_drivers): e1000.c e1000_hw.h
++$(e1000_drivers): %.o: e1000.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+@@ -103,28 +122,38 @@
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
++$(forcedeth_drivers): forcedeth.c
++$(forcedeth_drivers): %.o: forcedeth.c
++ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
+ #$(fa311_drivers): fa311.c
+ #$(fa311_drivers): %.o: fa311.c
+ # $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ # $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(i82586_drivers): i82586.c
+-$(i82586_drivers): %.o: i82586.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(i82586_drivers): i82586.c
++#$(i82586_drivers): %.o: i82586.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(lance_drivers): lance.c
+-$(lance_drivers): %.o: lance.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(lance_drivers): lance.c
++#$(lance_drivers): %.o: lance.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+ $(natsemi_drivers): natsemi.c
+ $(natsemi_drivers): %.o: natsemi.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(ni5010_drivers): ni5010.c
+-$(ni5010_drivers): %.o: ni5010.c
++#$(ni5010_drivers): ni5010.c
++#$(ni5010_drivers): %.o: ni5010.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++$(ns83820_drivers): ns83820.c
++$(ns83820_drivers): %.o: ns83820.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+@@ -133,8 +162,18 @@
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(otulip_drivers): otulip.c otulip.h
+-$(otulip_drivers): %.o: otulip.c
++#$(otulip_drivers): otulip.c otulip.h
++#$(otulip_drivers): %.o: otulip.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++$(pcnet32_drivers): pcnet32.c
++$(pcnet32_drivers): %.o: pcnet32.c
++ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++$(pnic_drivers): pnic.c
++$(pnic_drivers): %.o: pnic.c pnic_api.h
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+@@ -143,36 +182,56 @@
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(sis900_drivers): sis900.c
+-$(sis900_drivers): %.o: sis900.c sis900.h
++$(r8169_drivers): r8169.c
++$(r8169_drivers): %.o: r8169.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(sk_g16_drivers): sk_g16.c sk_g16.h
+-$(sk_g16_drivers): %.o: sk_g16.c
++$(sis900_drivers): sis900.c sis900.h
++$(sis900_drivers): %.o: sis900.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(smc9000_drivers): smc9000.c smc9000.h
+-$(smc9000_drivers): %.o: smc9000.c
++#$(sk_g16_drivers): sk_g16.c sk_g16.h
++#$(sk_g16_drivers): %.o: sk_g16.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++#$(smc9000_drivers): smc9000.c smc9000.h
++#$(smc9000_drivers): %.o: smc9000.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++$(sundance_drivers): sundance.c
++$(sundance_drivers): %.o: sundance.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(tiara_drivers): tiara.c
+-$(tiara_drivers): %.o: tiara.c
++$(tg3_drivers): tg3.c tg3.h
++$(tg3_drivers): %.o: tg3.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-#$(tlan_drivers): tlan.c
+-#$(tlan_drivers): %.o: tlan.c
++#$(tiara_drivers): tiara.c
++#$(tiara_drivers): %.o: tiara.c
+ # $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ # $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
++$(tlan_drivers): tlan.c tlan.h
++$(tlan_drivers): %.o: tlan.c
++ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
+ $(tulip_drivers): tulip.c
+ $(tulip_drivers): %.o: tulip.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
++$(undi_drivers): undi.c undi.h
++$(undi_drivers): %.o: undi.c
++ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
+ $(via_rhine_drivers): via-rhine.c
+ $(via_rhine_drivers): %.o: via-rhine.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+@@ -184,36 +243,45 @@
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+ # Per-object flags.
+-3c509_o_CFLAGS = -DINCLUDE_3C509=1
+-3c529_o_CFLAGS = -DINCLUDE_3C529=1
++#3c509_o_CFLAGS = -DINCLUDE_3C509=1
++#3c529_o_CFLAGS = -DINCLUDE_3C529=1
+ 3c595_o_CFLAGS = -DINCLUDE_3C595=1
+ 3c90x_o_CFLAGS = -DINCLUDE_3C90X=1
+-cs89x0_o_CFLAGS = -DINCLUDE_CS89X0=1
++#cs89x0_o_CFLAGS = -DINCLUDE_CS89X0=1
+ davicom_o_CFLAGS = -DINCLUDE_DAVICOM=1
+-depca_o_CFLAGS = -DINCLUDE_DEPCA=1
+-eepro_o_CFLAGS = -DINCLUDE_EEPRO=1
++#depca_o_CFLAGS = -DINCLUDE_DEPCA=1
++#eepro_o_CFLAGS = -DINCLUDE_EEPRO=1
++e1000_o_CFLAGS = -DINCLUDE_E1000=1
+ eepro100_o_CFLAGS = -DINCLUDE_EEPRO100=1
+ epic100_o_CFLAGS = -DINCLUDE_EPIC100=1
+ #fa311_o_CFLAGS = -DINCLUDE_FA311=1
+-3c507_o_CFLAGS = -DINCLUDE_3C507=1
+-exos205_o_CFLAGS = -DINCLUDE_EXOS205=1
+-ni5210_o_CFLAGS = -DINCLUDE_NI5210=1
+-lance_o_CFLAGS = -DINCLUDE_LANCE=1
+-ne2100_o_CFLAGS = -DINCLUDE_NE2100=1
+-ni6510_o_CFLAGS = -DINCLUDE_NI6510=1
++forcedeth_o_CFLAGS = -DINCLUDE_FORCEDETH=1
++#3c507_o_CFLAGS = -DINCLUDE_3C507=1
++#exos205_o_CFLAGS = -DINCLUDE_EXOS205=1
++#ni5210_o_CFLAGS = -DINCLUDE_NI5210=1
++#lance_o_CFLAGS = -DINCLUDE_LANCE=1
++#ne2100_o_CFLAGS = -DINCLUDE_NE2100=1
++#ni6510_o_CFLAGS = -DINCLUDE_NI6510=1
+ natsemi_o_CFLAGS = -DINCLUDE_NATSEMI=1
+-ni5010_o_CFLAGS = -DINCLUDE_NI5010=1
+-3c503_o_CFLAGS = -DINCLUDE_3C503=1
+-ne_o_CFLAGS = -DINCLUDE_NE=1
++#ni5010_o_CFLAGS = -DINCLUDE_NI5010=1
++#3c503_o_CFLAGS = -DINCLUDE_3C503=1
++#ne_o_CFLAGS = -DINCLUDE_NE=1
++ns83820_o_CFLAGS = -DINCLUDE_NS83820=1
+ ns8390_o_CFLAGS = -DINCLUDE_NS8390=1
+-wd_o_CFLAGS = -DINCLUDE_WD=1
+-otulip_o_CFLAGS = -DINCLUDE_OTULIP=1
++#wd_o_CFLAGS = -DINCLUDE_WD=1
++#otulip_o_CFLAGS = -DINCLUDE_OTULIP=1
++pcnet32_o_CFLAGS = -DINCLUDE_PCNET32=1
++pnic_o_CFLAGS = -DINCLUDE_PNIC=1
++r8169_o_CFLAGS = -DINCLUDE_R8169=1
+ rtl8139_o_CFLAGS = -DINCLUDE_RTL8139=1
+ sis900_o_CFLAGS = -DINCLUDE_SIS900=1
+-sk_g16_o_CFLAGS = -DINCLUDE_SK_G16=1
+-smc9000_o_CFLAGS = -DINCLUDE_SMC9000=1
+-tiara_o_CFLAGS = -DINCLUDE_TIARA=1
+-#tlan_o_CFLAGS = -DINCLUDE_TLAN=1
++#sk_g16_o_CFLAGS = -DINCLUDE_SK_G16=1
++#smc9000_o_CFLAGS = -DINCLUDE_SMC9000=1
++sundance_o_CFLAGS = -DINCLUDE_SUNDANCE=1
++#tiara_o_CFLAGS = -DINCLUDE_TIARA=1
++tg3_o_CFLAGS = -DINCLUDE_TG3=1
++tlan_o_CFLAGS = -DINCLUDE_TLAN=1
+ tulip_o_CFLAGS = -DINCLUDE_TULIP=1
++undi_o_CFLAGS = -DINCLUDE_UNDI=1
+ via_rhine_o_CFLAGS = -DINCLUDE_VIA_RHINE=1
+ w89c840_o_CFLAGS = -DINCLUDE_W89C840=1
+diff -Naur grub-0.97.orig/netboot/Makefile.in grub-0.97/netboot/Makefile.in
+--- grub-0.97.orig/netboot/Makefile.in 2005-05-08 02:42:35.000000000 +0000
++++ grub-0.97/netboot/Makefile.in 2005-09-01 00:14:15.000000000 +0000
+@@ -48,18 +47,51 @@
+ mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs
+ CONFIG_HEADER = $(top_builddir)/config.h
+ CONFIG_CLEAN_FILES =
+-LIBRARIES = $(noinst_LIBRARIES)
+ AR = ar
+ ARFLAGS = cru
++LIBRARIES = $(noinst_LIBRARIES)
+ libdrivers_a_AR = $(AR) $(ARFLAGS)
+ am_libdrivers_a_OBJECTS = libdrivers_a-config.$(OBJEXT) \
+- libdrivers_a-fsys_tftp.$(OBJEXT) libdrivers_a-main.$(OBJEXT) \
+- libdrivers_a-misc.$(OBJEXT) libdrivers_a-pci.$(OBJEXT) \
+- libdrivers_a-timer.$(OBJEXT)
++ libdrivers_a-fsys_tftp.$(OBJEXT) \
++ libdrivers_a-i386_timer.$(OBJEXT) libdrivers_a-misc.$(OBJEXT) \
++ libdrivers_a-nic.$(OBJEXT) libdrivers_a-pci.$(OBJEXT) \
++ libdrivers_a-pci_io.$(OBJEXT) libdrivers_a-timer.$(OBJEXT) \
++ libdrivers_a-pic8259.$(OBJEXT) libdrivers_a-basemem.$(OBJEXT)
+ libdrivers_a_OBJECTS = $(am_libdrivers_a_OBJECTS)
+ DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir)
+ depcomp = $(SHELL) $(top_srcdir)/depcomp
+ am__depfiles_maybe = depfiles
++@AMDEP_TRUE@DEP_FILES = ./$(DEPDIR)/libdrivers_a-3c595.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-3c90x.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-basemem.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-config.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-davicom.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-e1000.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-eepro100.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-epic100.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-forcedeth.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-fsys_tftp.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-i386_timer.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-misc.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-natsemi.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-nic.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-ns83820.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-ns8390.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-pci.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-pci_io.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-pcnet32.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-pic8259.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-pnic.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-pnic_api.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-r8169.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-rtl8139.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-sis900.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-tg3.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-timer.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-tlan.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-tulip.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-via-rhine.Po \
++@AMDEP_TRUE@ ./$(DEPDIR)/libdrivers_a-w89c840.Po
+ COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+ CCLD = $(CC)
+@@ -148,8 +180,6 @@
+ am__include = @am__include@
+ am__leading_dot = @am__leading_dot@
+ am__quote = @am__quote@
+-am__tar = @am__tar@
+-am__untar = @am__untar@
+ bindir = @bindir@
+ build = @build@
+ build_alias = @build_alias@
+@@ -186,16 +216,19 @@
+ # Don't build the netboot support by default.
+ @NETBOOT_SUPPORT_TRUE@LIBDRIVERS = libdrivers.a
+ noinst_LIBRARIES = $(LIBDRIVERS)
+-libdrivers_a_SOURCES = cards.h config.c etherboot.h \
+- fsys_tftp.c linux-asm-io.h linux-asm-string.h \
+- main.c misc.c nic.h osdep.h pci.c pci.h timer.c timer.h
+-
+-EXTRA_libdrivers_a_SOURCES = 3c509.c 3c509.h 3c595.c 3c595.h 3c90x.c \
+- cs89x0.c cs89x0.h davicom.c depca.c eepro.c eepro100.c \
+- epic100.c epic100.h fa311.c i82586.c lance.c natsemi.c \
+- ni5010.c ns8390.c ns8390.h otulip.c otulip.h rtl8139.c \
+- sis900.c sis900.h sk_g16.c sk_g16.h smc9000.c smc9000.h \
+- tiara.c tlan.c tulip.c via-rhine.c w89c840.c
++libdrivers_a_SOURCES = big_bswap.h bootp.h byteswap.h config.c cpu.h \
++ dev.h elf.h endian.h etherboot.h fsys_tftp.c grub.h \
++ i386_byteswap.h i386_elf.h i386_endian.h i386_timer.c \
++ if_arp.h if_ether.h igmp.h in.h io.h ip.h isa.h latch.h \
++ little_bswap.h misc.c nic.c nic.h osdep.h pci.c pci.h \
++ pci_ids.h pci_io.c stdint.h tftp.h timer.c timer.h \
++ types.h udp.h mii.h pic8259.c pic8259.h pxe.h basemem.c segoff.h
++
++EXTRA_libdrivers_a_SOURCES = 3c595.c 3c595.h 3c90x.c davicom.c \
++ e1000.c e1000_hw.h eepro100.c epic100.c epic100.h natsemi.c \
++ ns8390.c ns8390.h pcnet32.c rtl8139.c sis900.c sis900.h \
++ tg3.c tg3.h tlan.c tlan.h tulip.c via-rhine.c \
++ w89c840.c r8169.c forcedeth.c ns83820.c pnic.c pnic_api.c
+
+ libdrivers_a_CFLAGS = $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ -DFSYS_TFTP=1 $(NET_CFLAGS) $(NET_EXTRAFLAGS)
+@@ -203,69 +236,83 @@
+ # Filled by configure.
+ libdrivers_a_LIBADD = @NETBOOT_DRIVERS@
+ libdrivers_a_DEPENDENCIES = $(libdrivers_a_LIBADD)
+-EXTRA_DIST = README.netboot 3c90x.txt cs89x0.txt sis900.txt tulip.txt
++EXTRA_DIST = README.netboot
+
+ # These below are several special rules for the device drivers.
+ # We cannot use a simple rule for them...
+
+ # What objects are derived from a driver?
+-3c509_drivers = 3c509.o 3c529.o
++#3c509_drivers = 3c509.o 3c529.o
+ 3c595_drivers = 3c595.o
+ 3c90x_drivers = 3c90x.o
+-cs89x0_drivers = cs89x0.o
++#cs89x0_drivers = cs89x0.o
+ davicom_drivers = davicom.o
+-depca_drivers = depca.o
+-eepro_drivers = eepro.o
++#depca_drivers = depca.o
++#eepro_drivers = eepro.o
++e1000_drivers = e1000.o
+ eepro100_drivers = eepro100.o
+ epic100_drivers = epic100.o
+ #fa311_drivers = fa311.o
+-i82586_drivers = 3c507.o exos205.o ni5210.o
+-lance_drivers = lance.o ne2100.o ni6510.o
++forcedeth_drivers = forcedeth.o
++#i82586_drivers = 3c507.o exos205.o ni5210.o
++#lance_drivers = lance.o ne2100.o ni6510.o
+ natsemi_drivers = natsemi.o
+-ni5010_drivers = ni5010.o
++#ni5010_drivers = ni5010.o
++ns83820_drivers = ns83820.o
+ ns8390_drivers = 3c503.o ne.o ns8390.o wd.o
+-otulip_drivers = otulip.o
++#otulip_drivers = otulip.o
++pcnet32_drivers = pcnet32.o
++pnic_drivers = pnic.o
++r8169_drivers = r8169.o
+ rtl8139_drivers = rtl8139.o
+ sis900_drivers = sis900.o
+-sk_g16_drivers = sk_g16.o
+-smc9000_drivers = smc9000.o
+-tiara_drivers = tiara.o
+-#tlan_drivers = tlan.o
++#sk_g16_drivers = sk_g16.o
++#smc9000_drivers = smc9000.o
++tg3_drivers = tg3.o
++#tiara_drivers = tiara.o
++tlan_drivers = tlan.o
+ tulip_drivers = tulip.o
+ via_rhine_drivers = via_rhine.o
+ w89c840_drivers = w89c840.o
+
+ # Per-object flags.
+-3c509_o_CFLAGS = -DINCLUDE_3C509=1
+-3c529_o_CFLAGS = -DINCLUDE_3C529=1
++#3c509_o_CFLAGS = -DINCLUDE_3C509=1
++#3c529_o_CFLAGS = -DINCLUDE_3C529=1
+ 3c595_o_CFLAGS = -DINCLUDE_3C595=1
+ 3c90x_o_CFLAGS = -DINCLUDE_3C90X=1
+-cs89x0_o_CFLAGS = -DINCLUDE_CS89X0=1
++#cs89x0_o_CFLAGS = -DINCLUDE_CS89X0=1
+ davicom_o_CFLAGS = -DINCLUDE_DAVICOM=1
+-depca_o_CFLAGS = -DINCLUDE_DEPCA=1
+-eepro_o_CFLAGS = -DINCLUDE_EEPRO=1
++#depca_o_CFLAGS = -DINCLUDE_DEPCA=1
++#eepro_o_CFLAGS = -DINCLUDE_EEPRO=1
++e1000_o_CFLAGS = -DINCLUDE_E1000=1
+ eepro100_o_CFLAGS = -DINCLUDE_EEPRO100=1
+ epic100_o_CFLAGS = -DINCLUDE_EPIC100=1
+ #fa311_o_CFLAGS = -DINCLUDE_FA311=1
+-3c507_o_CFLAGS = -DINCLUDE_3C507=1
+-exos205_o_CFLAGS = -DINCLUDE_EXOS205=1
+-ni5210_o_CFLAGS = -DINCLUDE_NI5210=1
+-lance_o_CFLAGS = -DINCLUDE_LANCE=1
+-ne2100_o_CFLAGS = -DINCLUDE_NE2100=1
+-ni6510_o_CFLAGS = -DINCLUDE_NI6510=1
++forcedeth_o_CFLAGS = -DINCLUDE_FORCEDETH=1
++#3c507_o_CFLAGS = -DINCLUDE_3C507=1
++#exos205_o_CFLAGS = -DINCLUDE_EXOS205=1
++#ni5210_o_CFLAGS = -DINCLUDE_NI5210=1
++#lance_o_CFLAGS = -DINCLUDE_LANCE=1
++#ne2100_o_CFLAGS = -DINCLUDE_NE2100=1
++#ni6510_o_CFLAGS = -DINCLUDE_NI6510=1
+ natsemi_o_CFLAGS = -DINCLUDE_NATSEMI=1
+-ni5010_o_CFLAGS = -DINCLUDE_NI5010=1
+-3c503_o_CFLAGS = -DINCLUDE_3C503=1
+-ne_o_CFLAGS = -DINCLUDE_NE=1
++#ni5010_o_CFLAGS = -DINCLUDE_NI5010=1
++#3c503_o_CFLAGS = -DINCLUDE_3C503=1
++#ne_o_CFLAGS = -DINCLUDE_NE=1
++ns83820_o_CFLAGS = -DINCLUDE_NS83820=1
+ ns8390_o_CFLAGS = -DINCLUDE_NS8390=1
+-wd_o_CFLAGS = -DINCLUDE_WD=1
+-otulip_o_CFLAGS = -DINCLUDE_OTULIP=1
++#wd_o_CFLAGS = -DINCLUDE_WD=1
++#otulip_o_CFLAGS = -DINCLUDE_OTULIP=1
++pcnet32_o_CFLAGS = -DINCLUDE_PCNET32=1
++pnic_o_CFLAGS = -DINCLUDE_PNIC=1
++r8169_o_CFLAGS = -DINCLUDE_R8169=1
+ rtl8139_o_CFLAGS = -DINCLUDE_RTL8139=1
+ sis900_o_CFLAGS = -DINCLUDE_SIS900=1
+-sk_g16_o_CFLAGS = -DINCLUDE_SK_G16=1
+-smc9000_o_CFLAGS = -DINCLUDE_SMC9000=1
+-tiara_o_CFLAGS = -DINCLUDE_TIARA=1
+-#tlan_o_CFLAGS = -DINCLUDE_TLAN=1
++#sk_g16_o_CFLAGS = -DINCLUDE_SK_G16=1
++#smc9000_o_CFLAGS = -DINCLUDE_SMC9000=1
++#tiara_o_CFLAGS = -DINCLUDE_TIARA=1
++tg3_o_CFLAGS = -DINCLUDE_TG3=1
++tlan_o_CFLAGS = -DINCLUDE_TLAN=1
+ tulip_o_CFLAGS = -DINCLUDE_TULIP=1
+ via_rhine_o_CFLAGS = -DINCLUDE_VIA_RHINE=1
+ w89c840_o_CFLAGS = -DINCLUDE_W89C840=1
+@@ -316,32 +363,32 @@
+ distclean-compile:
+ -rm -f *.tab.c
+
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-3c509.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-3c595.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-3c90x.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-basemem.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-config.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-cs89x0.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-davicom.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-depca.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-eepro.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-e1000.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-eepro100.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-epic100.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-fa311.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-forcedeth.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-fsys_tftp.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-i82586.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-lance.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-main.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-i386_timer.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-misc.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-natsemi.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-ni5010.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-nic.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-ns83820.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-ns8390.Po@am__quote@
+-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-otulip.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-pci.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-pci_io.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-pcnet32.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-pic8259.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libdrivers_a-pnic.Po@am__quote@
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++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-r8169.Tpo" "$(DEPDIR)/libdrivers_a-r8169.Po"; else rm -f "$(DEPDIR)/libdrivers_a-r8169.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='r8169.c' object='libdrivers_a-r8169.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-r8169.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-r8169.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-r8169.o `test -f 'r8169.c' || echo '$(srcdir)/'`r8169.c
++
++libdrivers_a-r8169.obj: r8169.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-r8169.obj -MD -MP -MF "$(DEPDIR)/libdrivers_a-r8169.Tpo" -c -o libdrivers_a-r8169.obj `if test -f 'r8169.c'; then $(CYGPATH_W) 'r8169.c'; else $(CYGPATH_W) '$(srcdir)/r8169.c'; fi`; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-r8169.Tpo" "$(DEPDIR)/libdrivers_a-r8169.Po"; else rm -f "$(DEPDIR)/libdrivers_a-r8169.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='r8169.c' object='libdrivers_a-r8169.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-r8169.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-r8169.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-r8169.obj `if test -f 'r8169.c'; then $(CYGPATH_W) 'r8169.c'; else $(CYGPATH_W) '$(srcdir)/r8169.c'; fi`
++
++libdrivers_a-forcedeth.o: forcedeth.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-forcedeth.o -MD -MP -MF "$(DEPDIR)/libdrivers_a-forcedeth.Tpo" -c -o libdrivers_a-forcedeth.o `test -f 'forcedeth.c' || echo '$(srcdir)/'`forcedeth.c; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-forcedeth.Tpo" "$(DEPDIR)/libdrivers_a-forcedeth.Po"; else rm -f "$(DEPDIR)/libdrivers_a-forcedeth.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='forcedeth.c' object='libdrivers_a-forcedeth.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-forcedeth.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-forcedeth.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-forcedeth.o `test -f 'forcedeth.c' || echo '$(srcdir)/'`forcedeth.c
++
++libdrivers_a-forcedeth.obj: forcedeth.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-forcedeth.obj -MD -MP -MF "$(DEPDIR)/libdrivers_a-forcedeth.Tpo" -c -o libdrivers_a-forcedeth.obj `if test -f 'forcedeth.c'; then $(CYGPATH_W) 'forcedeth.c'; else $(CYGPATH_W) '$(srcdir)/forcedeth.c'; fi`; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-forcedeth.Tpo" "$(DEPDIR)/libdrivers_a-forcedeth.Po"; else rm -f "$(DEPDIR)/libdrivers_a-forcedeth.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='forcedeth.c' object='libdrivers_a-forcedeth.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-forcedeth.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-forcedeth.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-forcedeth.obj `if test -f 'forcedeth.c'; then $(CYGPATH_W) 'forcedeth.c'; else $(CYGPATH_W) '$(srcdir)/forcedeth.c'; fi`
++
++libdrivers_a-ns83820.o: ns83820.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-ns83820.o -MD -MP -MF "$(DEPDIR)/libdrivers_a-ns83820.Tpo" -c -o libdrivers_a-ns83820.o `test -f 'ns83820.c' || echo '$(srcdir)/'`ns83820.c; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-ns83820.Tpo" "$(DEPDIR)/libdrivers_a-ns83820.Po"; else rm -f "$(DEPDIR)/libdrivers_a-ns83820.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ns83820.c' object='libdrivers_a-ns83820.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-ns83820.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-ns83820.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-ns83820.o `test -f 'ns83820.c' || echo '$(srcdir)/'`ns83820.c
++
++libdrivers_a-ns83820.obj: ns83820.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-ns83820.obj -MD -MP -MF "$(DEPDIR)/libdrivers_a-ns83820.Tpo" -c -o libdrivers_a-ns83820.obj `if test -f 'ns83820.c'; then $(CYGPATH_W) 'ns83820.c'; else $(CYGPATH_W) '$(srcdir)/ns83820.c'; fi`; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-ns83820.Tpo" "$(DEPDIR)/libdrivers_a-ns83820.Po"; else rm -f "$(DEPDIR)/libdrivers_a-ns83820.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ns83820.c' object='libdrivers_a-ns83820.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-ns83820.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-ns83820.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-ns83820.obj `if test -f 'ns83820.c'; then $(CYGPATH_W) 'ns83820.c'; else $(CYGPATH_W) '$(srcdir)/ns83820.c'; fi`
++
++libdrivers_a-pnic.o: pnic.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-pnic.o -MD -MP -MF "$(DEPDIR)/libdrivers_a-pnic.Tpo" -c -o libdrivers_a-pnic.o `test -f 'pnic.c' || echo '$(srcdir)/'`pnic.c; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-pnic.Tpo" "$(DEPDIR)/libdrivers_a-pnic.Po"; else rm -f "$(DEPDIR)/libdrivers_a-pnic.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pnic.c' object='libdrivers_a-pnic.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-pnic.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-pnic.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-pnic.o `test -f 'pnic.c' || echo '$(srcdir)/'`pnic.c
++
++libdrivers_a-pnic.obj: pnic.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-pnic.obj -MD -MP -MF "$(DEPDIR)/libdrivers_a-pnic.Tpo" -c -o libdrivers_a-pnic.obj `if test -f 'pnic.c'; then $(CYGPATH_W) 'pnic.c'; else $(CYGPATH_W) '$(srcdir)/pnic.c'; fi`; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-pnic.Tpo" "$(DEPDIR)/libdrivers_a-pnic.Po"; else rm -f "$(DEPDIR)/libdrivers_a-pnic.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pnic.c' object='libdrivers_a-pnic.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-pnic.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-pnic.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-pnic.obj `if test -f 'pnic.c'; then $(CYGPATH_W) 'pnic.c'; else $(CYGPATH_W) '$(srcdir)/pnic.c'; fi`
++
++libdrivers_a-pnic_api.o: pnic_api.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-pnic_api.o -MD -MP -MF "$(DEPDIR)/libdrivers_a-pnic_api.Tpo" -c -o libdrivers_a-pnic_api.o `test -f 'pnic_api.c' || echo '$(srcdir)/'`pnic_api.c; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-pnic_api.Tpo" "$(DEPDIR)/libdrivers_a-pnic_api.Po"; else rm -f "$(DEPDIR)/libdrivers_a-pnic_api.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pnic_api.c' object='libdrivers_a-pnic_api.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-pnic_api.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-pnic_api.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-pnic_api.o `test -f 'pnic_api.c' || echo '$(srcdir)/'`pnic_api.c
++
++libdrivers_a-pnic_api.obj: pnic_api.c
++@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -MT libdrivers_a-pnic_api.obj -MD -MP -MF "$(DEPDIR)/libdrivers_a-pnic_api.Tpo" -c -o libdrivers_a-pnic_api.obj `if test -f 'pnic_api.c'; then $(CYGPATH_W) 'pnic_api.c'; else $(CYGPATH_W) '$(srcdir)/pnic_api.c'; fi`; \
++@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libdrivers_a-pnic_api.Tpo" "$(DEPDIR)/libdrivers_a-pnic_api.Po"; else rm -f "$(DEPDIR)/libdrivers_a-pnic_api.Tpo"; exit 1; fi
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pnic_api.c' object='libdrivers_a-pnic_api.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/libdrivers_a-pnic_api.Po' tmpdepfile='$(DEPDIR)/libdrivers_a-pnic_api.TPo' @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libdrivers_a_CFLAGS) $(CFLAGS) -c -o libdrivers_a-pnic_api.obj `if test -f 'pnic_api.c'; then $(CYGPATH_W) 'pnic_api.c'; else $(CYGPATH_W) '$(srcdir)/pnic_api.c'; fi`
+
+ ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+@@ -817,11 +927,9 @@
+ done | \
+ $(AWK) ' { files[$$0] = 1; } \
+ END { for (i in files) print i; }'`; \
+- if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \
+- test -n "$$unique" || unique=$$empty_fix; \
+- $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+- $$tags $$unique; \
+- fi
++ test -z "$(ETAGS_ARGS)$$tags$$unique" \
++ || $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
++ $$tags $$unique
+ ctags: CTAGS
+ CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+@@ -895,7 +1003,7 @@
+ clean-generic:
+
+ distclean-generic:
+- -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
++ -rm -f $(CONFIG_CLEAN_FILES)
+
+ maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+@@ -962,10 +1070,10 @@
+
+
+ # Is it really necessary to specify dependecies explicitly?
+-$(3c509_drivers): 3c509.c 3c509.h
+-$(3c509_drivers): %.o: 3c509.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(3c509_drivers): 3c509.c 3c509.h
++#$(3c509_drivers): %.o: 3c509.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+ $(3c595_drivers): 3c595.c 3c595.h
+ $(3c595_drivers): %.o: 3c595.c
+@@ -977,23 +1085,28 @@
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(cs89x0_drivers): cs89x0.c cs89x0.h
+-$(cs89x0_drivers): %.o: cs89x0.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(cs89x0_drivers): cs89x0.c cs89x0.h
++#$(cs89x0_drivers): %.o: cs89x0.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+ $(davicom_drivers): davicom.c
+ $(davicom_drivers): %.o: davicom.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(depca_drivers): depca.c
+-$(depca_drivers): %.o: depca.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(depca_drivers): depca.c
++#$(depca_drivers): %.o: depca.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(eepro_drivers): eepro.c
+-$(eepro_drivers): %.o: eepro.c
++#$(eepro_drivers): eepro.c
++#$(eepro_drivers): %.o: eepro.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++$(e1000_drivers): e1000.c e1000_hw.h
++$(e1000_drivers): %.o: e1000.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+@@ -1007,28 +1120,38 @@
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
++$(forcedeth_drivers): forcedeth.c
++$(forcedeth_drivers): %.o: forcedeth.c
++ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
+ #$(fa311_drivers): fa311.c
+ #$(fa311_drivers): %.o: fa311.c
+ # $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ # $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(i82586_drivers): i82586.c
+-$(i82586_drivers): %.o: i82586.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(i82586_drivers): i82586.c
++#$(i82586_drivers): %.o: i82586.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(lance_drivers): lance.c
+-$(lance_drivers): %.o: lance.c
+- $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+- $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++#$(lance_drivers): lance.c
++#$(lance_drivers): %.o: lance.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+ $(natsemi_drivers): natsemi.c
+ $(natsemi_drivers): %.o: natsemi.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(ni5010_drivers): ni5010.c
+-$(ni5010_drivers): %.o: ni5010.c
++#$(ni5010_drivers): ni5010.c
++#$(ni5010_drivers): %.o: ni5010.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++$(ns83820_drivers): ns83820.c
++$(ns83820_drivers): %.o: ns83820.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+@@ -1037,41 +1160,62 @@
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(otulip_drivers): otulip.c otulip.h
+-$(otulip_drivers): %.o: otulip.c
++#$(otulip_drivers): otulip.c otulip.h
++#$(otulip_drivers): %.o: otulip.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++$(pcnet32_drivers): pcnet32.c
++$(pcnet32_drivers): %.o: pcnet32.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(rtl8139_drivers): rtl8139.c
+-$(rtl8139_drivers): %.o: rtl8139.c
++$(pnic_drivers): pnic.c
++$(pnic_drivers): %.o: pnic.c pnic_api.h
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(sis900_drivers): sis900.c
+-$(sis900_drivers): %.o: sis900.c sis900.h
++$(rtl8139_drivers): rtl8139.c
++$(rtl8139_drivers): %.o: rtl8139.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(sk_g16_drivers): sk_g16.c sk_g16.h
+-$(sk_g16_drivers): %.o: sk_g16.c
++$(r8169_drivers): r8169.c
++$(r8169_drivers): %.o: r8169.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(smc9000_drivers): smc9000.c smc9000.h
+-$(smc9000_drivers): %.o: smc9000.c
++$(sis900_drivers): sis900.c sis900.h
++$(sis900_drivers): %.o: sis900.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-$(tiara_drivers): tiara.c
+-$(tiara_drivers): %.o: tiara.c
++#$(sk_g16_drivers): sk_g16.c sk_g16.h
++#$(sk_g16_drivers): %.o: sk_g16.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++#$(smc9000_drivers): smc9000.c smc9000.h
++#$(smc9000_drivers): %.o: smc9000.c
++# $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++# $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
++
++$(tg3_drivers): tg3.c tg3.h
++$(tg3_drivers): %.o: tg3.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
+-#$(tlan_drivers): tlan.c
+-#$(tlan_drivers): %.o: tlan.c
++#$(tiara_drivers): tiara.c
++#$(tiara_drivers): %.o: tiara.c
+ # $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+ # $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
+
++$(tlan_drivers): tlan.c tlan.h
++$(tlan_drivers): %.o: tlan.c
++ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
++ $(NET_EXTRAFLAGS) $($(basename $@)_o_CFLAGS) -o $@ -c $<
++
+ $(tulip_drivers): tulip.c
+ $(tulip_drivers): %.o: tulip.c
+ $(COMPILE) $(STAGE2_CFLAGS) -fno-builtin -nostdinc \
+diff -Naur grub-0.97.orig/netboot/basemem.c grub-0.97/netboot/basemem.c
+--- grub-0.97.orig/netboot/basemem.c 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/basemem.c 2005-08-31 19:24:28.000000000 +0000
+@@ -0,0 +1,178 @@
++#include "etherboot.h"
++#define DEBUG_BASEMEM
++/* Routines to allocate base memory in a BIOS-compatible way, by
++ * updating the Free Base Memory Size counter at 40:13h.
++ *
++ * Michael Brown <mbrown@fensystems.co.uk> (mcb30)
++ * $Id: grub-0.95-diskless-patch-2-undi.patch,v 1.1.1.1 2005/06/14 08:18:50 wesolows Exp $
++ */
++
++#define fbms ( ( uint16_t * ) phys_to_virt ( 0x413 ) )
++#define BASE_MEMORY_MAX ( 640 )
++#define FREE_BLOCK_MAGIC ( ('!'<<0) + ('F'<<8) + ('R'<<16) + ('E'<<24) )
++
++typedef struct free_base_memory_block {
++ uint32_t magic;
++ uint16_t size_kb;
++} free_base_memory_block_t;
++
++/* Return amount of free base memory in bytes
++ */
++
++uint32_t get_free_base_memory ( void ) {
++ return *fbms << 10;
++}
++
++/* Adjust the real mode stack pointer. We keep the real mode stack at
++ * the top of free base memory, rather than allocating space for it.
++ */
++
++inline void adjust_real_mode_stack ( void ) {
++/* real_mode_stack = ( *fbms << 10 ); */
++}
++
++/* Allocate N bytes of base memory. Amount allocated will be rounded
++ * up to the nearest kB, since that's the granularity of the BIOS FBMS
++ * counter. Returns NULL if memory cannot be allocated.
++ */
++
++void * allot_base_memory ( size_t size ) {
++ uint16_t size_kb = ( size + 1023 ) >> 10;
++ void *ptr = NULL;
++
++#ifdef DEBUG_BASEMEM
++ printf ( "Trying to allocate %d kB of base memory, %d kB free\n",
++ size_kb, *fbms );
++#endif
++
++ /* Free up any unused memory before we start */
++ free_unused_base_memory();
++
++ /* Check available base memory */
++ if ( size_kb > *fbms ) { return NULL; }
++
++ /* Reduce available base memory */
++ *fbms -= size_kb;
++
++ /* Calculate address of memory allocated */
++ ptr = phys_to_virt ( *fbms << 10 );
++
++#ifdef DEBUG_BASEMEM
++ /* Zero out memory. We do this so that allocation of
++ * already-used space will show up in the form of a crash as
++ * soon as possible.
++ */
++ memset ( ptr, 0, size_kb << 10 );
++#endif
++
++ /* Adjust real mode stack pointer */
++ adjust_real_mode_stack ();
++
++ return ptr;
++}
++
++/* Free base memory allocated by allot_base_memory. The BIOS provides
++ * nothing better than a LIFO mechanism for freeing memory (i.e. it
++ * just has the single "total free memory" counter), but we improve
++ * upon this slightly; as long as you free all the allotted blocks, it
++ * doesn't matter what order you free them in. (This will only work
++ * for blocks that are freed via forget_base_memory()).
++ *
++ * Yes, it's annoying that you have to remember the size of the blocks
++ * you've allotted. However, since our granularity of allocation is
++ * 1K, the alternative is to risk wasting the occasional kB of base
++ * memory, which is a Bad Thing. Really, you should be using as
++ * little base memory as possible, so consider the awkwardness of the
++ * API to be a feature! :-)
++ */
++
++void forget_base_memory ( void *ptr, size_t size ) {
++ uint16_t remainder = virt_to_phys(ptr) & 1023;
++ uint16_t size_kb = ( size + remainder + 1023 ) >> 10;
++ free_base_memory_block_t *free_block =
++ ( free_base_memory_block_t * ) ( ptr - remainder );
++
++ if ( ( ptr == NULL ) || ( size == 0 ) ) { return; }
++
++#ifdef DEBUG_BASEMEM
++ printf ( "Trying to free %d bytes base memory at 0x%x\n",
++ size, virt_to_phys ( ptr ) );
++ if ( remainder > 0 ) {
++ printf ( "WARNING: destructively expanding free block "
++ "downwards to 0x%x\n",
++ virt_to_phys ( ptr - remainder ) );
++ }
++#endif
++
++ /* Mark every kilobyte within this block as free. This is
++ * overkill for normal purposes, but helps when something has
++ * allocated base memory with a granularity finer than the
++ * BIOS granularity of 1kB. PXE ROMs tend to do this when
++ * they allocate their own memory. This method allows us to
++ * free their blocks (admittedly in a rather dangerous,
++ * tread-on-anything-either-side sort of way, but there's no
++ * other way to do it).
++ *
++ * Since we're marking every kB as free, there's actually no
++ * need for recording the size of the blocks. However, we
++ * keep this in so that debug messages are friendlier. It
++ * probably adds around 8 bytes to the overall code size.
++ */
++ while ( size_kb > 0 ) {
++ /* Mark this block as unused */
++ free_block->magic = FREE_BLOCK_MAGIC;
++ free_block->size_kb = size_kb;
++ /* Move up by 1 kB */
++ (void *)(free_block += ( 1 << 10 ));
++ size_kb--;
++ }
++
++ /* Free up unused base memory */
++ free_unused_base_memory();
++}
++
++/* Do the actual freeing of memory. This is split out from
++ * forget_base_memory() so that it may be called separately. It
++ * should be called whenever base memory is deallocated by an external
++ * entity (if we can detect that it has done so) so that we get the
++ * chance to free up our own blocks.
++ */
++void free_unused_base_memory ( void ) {
++ free_base_memory_block_t *free_block = NULL;
++
++ /* Try to release memory back to the BIOS. Free all
++ * consecutive blocks marked as free.
++ */
++ while ( 1 ) {
++ /* Calculate address of next potential free block */
++ free_block = ( free_base_memory_block_t * )
++ phys_to_virt ( *fbms << 10 );
++
++ /* Stop processing if we're all the way up to 640K or
++ * if this is not a free block
++ */
++ if ( ( *fbms == BASE_MEMORY_MAX ) ||
++ ( free_block->magic != FREE_BLOCK_MAGIC ) ) {
++ break;
++ }
++
++ /* Return memory to BIOS */
++ *fbms += free_block->size_kb;
++
++#ifdef DEBUG_BASEMEM
++ printf ( "Freed %d kB base memory, %d kB now free\n",
++ free_block->size_kb, *fbms );
++
++ /* Zero out freed block. We do this in case
++ * the block contained any structures that
++ * might be located by scanning through
++ * memory.
++ */
++ memset ( free_block, 0, free_block->size_kb << 10 );
++#endif
++ }
++
++ /* Adjust real mode stack pointer */
++ adjust_real_mode_stack ();
++}
++
+diff -Naur grub-0.97.orig/netboot/big_bswap.h grub-0.97/netboot/big_bswap.h
+--- grub-0.97.orig/netboot/big_bswap.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/big_bswap.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,17 @@
++#ifndef ETHERBOOT_BIG_BSWAP_H
++#define ETHERBOOT_BIG_BSWAP_H
++
++#define ntohl(x) (x)
++#define htonl(x) (x)
++#define ntohs(x) (x)
++#define htons(x) (x)
++#define cpu_to_le32(x) __bswap_32(x)
++#define cpu_to_le16(x) __bswap_16(x)
++#define cpu_to_be32(x) (x)
++#define cpu_to_be16(x) (x)
++#define le32_to_cpu(x) __bswap_32(x)
++#define le16_to_cpu(x) __bswap_16(x)
++#define be32_to_cpu(x) (x)
++#define be16_to_cpu(x) (x)
++
++#endif /* ETHERBOOT_BIG_BSWAP_H */
+diff -Naur grub-0.97.orig/netboot/bootp.h grub-0.97/netboot/bootp.h
+--- grub-0.97.orig/netboot/bootp.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/bootp.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,182 @@
++#ifndef _BOOTP_H
++#define _BOOTP_H
++
++#include "if_ether.h"
++#include "ip.h"
++#include "udp.h"
++
++#ifndef MAX_BOOTP_RETRIES
++#define MAX_BOOTP_RETRIES 20
++#endif
++
++#ifdef ALTERNATE_DHCP_PORTS_1067_1068
++#undef NON_STANDARD_BOOTP_SERVER
++#define NON_STANDARD_BOOTP_SERVER 1067
++#undef NON_STANDARD_BOOTP_CLIENT
++#define NON_STANDARD_BOOTP_CLIENT 1068
++#endif
++
++#ifdef NON_STANDARD_BOOTP_SERVER
++#define BOOTP_SERVER NON_STANDARD_BOOTP_SERVER
++#else
++#define BOOTP_SERVER 67
++#endif
++#ifdef NON_STANDARD_BOOTP_CLIENT
++#define BOOTP_CLIENT NON_STANDARD_BOOTP_CLIENT
++#else
++#define BOOTP_CLIENT 68
++#endif
++
++#define BOOTP_REQUEST 1
++#define BOOTP_REPLY 2
++
++#define TAG_LEN(p) (*((p)+1))
++#define RFC1533_COOKIE 99, 130, 83, 99
++#define RFC1533_PAD 0
++#define RFC1533_NETMASK 1
++#define RFC1533_TIMEOFFSET 2
++#define RFC1533_GATEWAY 3
++#define RFC1533_TIMESERVER 4
++#define RFC1533_IEN116NS 5
++#define RFC1533_DNS 6
++#define RFC1533_LOGSERVER 7
++#define RFC1533_COOKIESERVER 8
++#define RFC1533_LPRSERVER 9
++#define RFC1533_IMPRESSSERVER 10
++#define RFC1533_RESOURCESERVER 11
++#define RFC1533_HOSTNAME 12
++#define RFC1533_BOOTFILESIZE 13
++#define RFC1533_MERITDUMPFILE 14
++#define RFC1533_DOMAINNAME 15
++#define RFC1533_SWAPSERVER 16
++#define RFC1533_ROOTPATH 17
++#define RFC1533_EXTENSIONPATH 18
++#define RFC1533_IPFORWARDING 19
++#define RFC1533_IPSOURCEROUTING 20
++#define RFC1533_IPPOLICYFILTER 21
++#define RFC1533_IPMAXREASSEMBLY 22
++#define RFC1533_IPTTL 23
++#define RFC1533_IPMTU 24
++#define RFC1533_IPMTUPLATEAU 25
++#define RFC1533_INTMTU 26
++#define RFC1533_INTLOCALSUBNETS 27
++#define RFC1533_INTBROADCAST 28
++#define RFC1533_INTICMPDISCOVER 29
++#define RFC1533_INTICMPRESPOND 30
++#define RFC1533_INTROUTEDISCOVER 31
++#define RFC1533_INTROUTESOLICIT 32
++#define RFC1533_INTSTATICROUTES 33
++#define RFC1533_LLTRAILERENCAP 34
++#define RFC1533_LLARPCACHETMO 35
++#define RFC1533_LLETHERNETENCAP 36
++#define RFC1533_TCPTTL 37
++#define RFC1533_TCPKEEPALIVETMO 38
++#define RFC1533_TCPKEEPALIVEGB 39
++#define RFC1533_NISDOMAIN 40
++#define RFC1533_NISSERVER 41
++#define RFC1533_NTPSERVER 42
++#define RFC1533_VENDOR 43
++#define RFC1533_NBNS 44
++#define RFC1533_NBDD 45
++#define RFC1533_NBNT 46
++#define RFC1533_NBSCOPE 47
++#define RFC1533_XFS 48
++#define RFC1533_XDM 49
++#ifndef NO_DHCP_SUPPORT
++#define RFC2132_REQ_ADDR 50
++#define RFC2132_MSG_TYPE 53
++#define RFC2132_SRV_ID 54
++#define RFC2132_PARAM_LIST 55
++#define RFC2132_MAX_SIZE 57
++#define RFC2132_VENDOR_CLASS_ID 60
++
++#define DHCPDISCOVER 1
++#define DHCPOFFER 2
++#define DHCPREQUEST 3
++#define DHCPACK 5
++#endif /* NO_DHCP_SUPPORT */
++
++#define RFC1533_VENDOR_MAJOR 0
++#define RFC1533_VENDOR_MINOR 0
++
++#define RFC1533_VENDOR_MAGIC 128
++#define RFC1533_VENDOR_ADDPARM 129
++#define RFC1533_VENDOR_ETHDEV 130
++#ifdef IMAGE_FREEBSD
++#define RFC1533_VENDOR_HOWTO 132
++#define RFC1533_VENDOR_KERNEL_ENV 133
++#endif
++#define RFC1533_VENDOR_ETHERBOOT_ENCAP 150
++#define RFC1533_VENDOR_MNUOPTS 160
++#define RFC1533_VENDOR_NIC_DEV_ID 175
++#define RFC1533_VENDOR_SELECTION 176
++#define RFC1533_VENDOR_ARCH 177
++#define RFC1533_VENDOR_MOTD 184
++#define RFC1533_VENDOR_NUMOFMOTD 8
++#define RFC1533_VENDOR_IMG 192
++#define RFC1533_VENDOR_NUMOFIMG 16
++
++#define RFC1533_VENDOR_CONFIGFILE 150
++
++#define RFC1533_END 255
++
++#define BOOTP_VENDOR_LEN 64
++
++#define DHCP_OPT_LEN 312
++
++/* Format of a bootp packet */
++struct bootp_t {
++ uint8_t bp_op;
++ uint8_t bp_htype;
++ uint8_t bp_hlen;
++ uint8_t bp_hops;
++ uint32_t bp_xid;
++ uint16_t bp_secs;
++ uint16_t unused;
++ in_addr bp_ciaddr;
++ in_addr bp_yiaddr;
++ in_addr bp_siaddr;
++ in_addr bp_giaddr;
++ uint8_t bp_hwaddr[16];
++ uint8_t bp_sname[64];
++ char bp_file[128];
++ uint8_t bp_vend[BOOTP_VENDOR_LEN];
++};
++
++struct dhcp_t {
++ uint8_t bp_op;
++ uint8_t bp_htype;
++ uint8_t bp_hlen;
++ uint8_t bp_hops;
++ uint32_t bp_xid;
++ uint16_t bp_secs;
++ uint16_t bp_flag;
++ in_addr bp_ciaddr;
++ in_addr bp_yiaddr;
++ in_addr bp_siaddr;
++ in_addr bp_giaddr;
++ uint8_t bp_hwaddr[16];
++ uint8_t bp_sname[64];
++ char bp_file[128];
++ uint8_t bp_vend[DHCP_OPT_LEN];
++};
++
++/* Format of a bootp IP packet */
++struct bootpip_t
++{
++ struct iphdr ip;
++ struct udphdr udp;
++ struct bootp_t bp;
++};
++struct dhcpip_t
++{
++ struct iphdr ip;
++ struct udphdr udp;
++ struct dhcp_t bp;
++};
++
++#define MAX_RFC1533_VENDLEN (ETH_MAX_MTU - sizeof(struct bootpip_t) + BOOTP_VENDOR_LEN)
++
++#define BOOTP_DATA_ADDR (&bootp_data)
++
++#endif /* _BOOTP_H */
+diff -Naur grub-0.97.orig/netboot/byteswap.h grub-0.97/netboot/byteswap.h
+--- grub-0.97.orig/netboot/byteswap.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/byteswap.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,20 @@
++#ifndef ETHERBOOT_BYTESWAP_H
++#define ETHERBOOT_BYTESWAP_H
++
++#include "endian.h"
++#include "i386_byteswap.h"
++
++#if __BYTE_ORDER == __LITTLE_ENDIAN
++#include "little_bswap.h"
++#endif
++#if __BYTE_ORDER == __BIG_ENDIAN
++#include "big_bswap.h"
++#endif
++
++/* Make routines available to all */
++#define swap32(x) __bswap_32(x)
++#define swap16(x) __bswap_16(x)
++#define bswap_32(x) __bswap_32(x)
++#define bswap_16(x) __bswap_16(x)
++
++#endif /* ETHERBOOT_BYTESWAP_H */
+diff -Naur grub-0.97.orig/netboot/cards.h grub-0.97/netboot/cards.h
+--- grub-0.97.orig/netboot/cards.h 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/cards.h 1970-01-01 00:00:00.000000000 +0000
+@@ -1,183 +0,0 @@
+-#ifndef CARDS_H
+-#define CARDS_H
+-
+-/*
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2, or (at
+- * your option) any later version.
+- */
+-
+-#include "nic.h"
+-
+-/* OK, this is how the PCI support hack works: if pci.h is included before
+- * this file is included, assume that the driver supports PCI. This means that
+- * this file is usually included last. */
+-
+-#ifdef PCI_H
+-#define PCI_ARG(x) ,x
+-#else
+-#define PCI_ARG(x)
+-#endif
+-
+-#ifdef INCLUDE_WD
+-extern struct nic *wd_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_3C503
+-extern struct nic *t503_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_VIA_RHINE
+-extern struct nic *rhine_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_NE
+-extern struct nic *ne_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_NS8390
+-extern struct nic *nepci_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_3C509
+-extern struct nic *t509_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_3C529
+-extern struct nic *t529_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_3C595
+-extern struct nic *t595_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_3C90X
+-extern struct nic *a3c90x_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_EEPRO
+-extern struct nic *eepro_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_EEPRO100
+-extern struct nic *eepro100_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_EPIC100
+-extern struct nic *epic100_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_OTULIP
+-extern struct nic *otulip_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_TULIP
+-extern struct nic *tulip_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_DAVICOM
+-extern struct nic *davicom_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_CS89X0
+-extern struct nic *cs89x0_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_LANCE
+-extern struct nic *lancepci_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_NE2100
+-extern struct nic *ne2100_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_NI6510
+-extern struct nic *ni6510_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_SK_G16
+-extern struct nic *SK_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_3C507
+-extern struct nic *t507_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_NI5010
+-extern struct nic *ni5010_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_NI5210
+-extern struct nic *ni5210_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_EXOS205
+-extern struct nic *exos205_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_SMC9000
+-extern struct nic *smc9000_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_TIARA
+-extern struct nic *tiara_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_DEPCA
+-extern struct nic *depca_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_RTL8139
+-extern struct nic *rtl8139_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_W89C840
+-extern struct nic *w89c840_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_SIS900
+-extern struct nic *sis900_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_NATSEMI
+-extern struct nic *natsemi_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#ifdef INCLUDE_TLAN
+-extern struct nic *tlan_probe(struct nic *, unsigned short *
+- PCI_ARG(struct pci_device *));
+-#endif
+-
+-#endif /* CARDS_H */
+diff -Naur grub-0.97.orig/netboot/config.c grub-0.97/netboot/config.c
+--- grub-0.97.orig/netboot/config.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/config.c 2005-08-31 19:03:35.000000000 +0000
+@@ -1,598 +1,165 @@
+ /*
+- * GRUB -- GRand Unified Bootloader
+- * Copyright (C) 2001,2002 Free Software Foundation, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+- */
+-
+-/* Based on "src/config.c" in etherboot-5.0.5. */
+-
+-/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+-#define GRUB 1
+-#include <etherboot.h>
+-#include <nic.h>
++#include "grub.h"
++#include "pci.h"
++#include "isa.h"
++#include "nic.h"
+
+-#undef INCLUDE_PCI
+-#if defined(INCLUDE_NS8390) || defined(INCLUDE_EEPRO100) || defined(INCLUDE_LANCE) || defined(INCLUDE_EPIC100) || defined(INCLUDE_TULIP) || defined(INCLUDE_OTULIP) || defined(INCLUDE_3C90X) || defined(INCLUDE_3C595) || defined(INCLUDE_RTL8139) || defined(INCLUDE_VIA_RHINE) || defined(INCLUDE_W89C840) || defined(INCLUDE_DAVICOM) || defined(INCLUDE_SIS900) || defined(INCLUDE_NATSEMI) || defined(INCLUDE_TLAN)
+- /* || others later */
+-# define INCLUDE_PCI
+-# include <pci.h>
+-static unsigned short pci_ioaddrs[16];
+-
+-static struct pci_device pci_nic_list[] =
++#ifdef CONFIG_PCI
++static int pci_probe(struct dev *dev, const char *type_name)
+ {
+-#ifdef INCLUDE_NS8390
+- { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8029,
+- "Realtek 8029", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940,
+- "Winbond NE2000-PCI", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_COMPEX, PCI_DEVICE_ID_COMPEX_RL2000,
+- "Compex ReadyLink 2000", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_KTI, PCI_DEVICE_ID_KTI_ET32P2,
+- "KTI ET32P2", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_NETVIN, PCI_DEVICE_ID_NETVIN_NV5000SC,
+- "NetVin NV5000SC", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_HT80232,
+- "Holtek HT80232", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_3C90X
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900TPO,
+- "3Com900-TPO", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900COMBO,
+- "3Com900-Combo", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905TX,
+- "3Com905-TX", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905T4,
+- "3Com905-T4", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9004,
+- "3Com900B-TPO", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9005,
+- "3Com900B-Combo", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9006,
+- "3Com900B-2/T", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x900A,
+- "3Com900B-FL", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905B_TX,
+- "3Com905B-TX", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9056,
+- "3Com905B-T4", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x905A,
+- "3Com905B-FL", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C_TXM,
+- "3Com905C-TXM", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9800,
+- "3Com980-Cyclone", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9805,
+- "3Com9805", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x7646,
+- "3CSOHO100-TX", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_3C595
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C590,
+- "3Com590", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C595,
+- "3Com595", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C595_1,
+- "3Com595", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C595_2,
+- "3Com595", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900TPO,
+- "3Com900-TPO", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900COMBO,
+- "3Com900-Combo", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9004,
+- "3Com900B-TPO", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9005,
+- "3Com900B-Combo", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9006,
+- "3Com900B-2/T", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x900A,
+- "3Com900B-FL", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9800,
+- "3Com980-Cyclone", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x9805,
+- "3Com9805", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_3COM, 0x7646,
+- "3CSOHO100-TX", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_EEPRO100
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557,
+- "Intel EtherExpressPro100", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER,
+- "Intel EtherExpressPro100 82559ER", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ID1029,
+- "Intel EtherExpressPro100 ID1029", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ID1030,
+- "Intel Corporation 82559 InBusiness 10/100", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82562,
+- "Intel EtherExpressPro100 82562EM", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_EPIC100
+- { PCI_VENDOR_ID_SMC, PCI_DEVICE_ID_SMC_EPIC100,
+- "SMC EtherPowerII", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_LANCE
+- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
+- "AMD Lance/PCI", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_AMD_HOMEPNA, PCI_DEVICE_ID_AMD_HOMEPNA,
+- "AMD Lance/HomePNA", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_RTL8139
+- { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
+- "Realtek 8139", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DFE530TXP,
+- "DFE530TX+/DFE538TX", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_SMC_1211, PCI_DEVICE_ID_SMC_1211,
+- "SMC EZ10/100", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_OTULIP
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
+- "Digital Tulip", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
+- "Digital Tulip Fast", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
+- "Digital Tulip+", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
+- "Digital Tulip 21142", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_TULIP
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
+- "Digital Tulip", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
+- "Digital Tulip Fast", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
+- "Digital Tulip+", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
+- "Digital Tulip 21142", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_MACRONIX, PCI_DEVICE_ID_MX987x5,
+- "Macronix MX987x5", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LC82C115,
+- "LinkSys LNE100TX", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_DEC_TULIP,
+- "Netgear FA310TX", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9102,
+- "Davicom 9102", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9009,
+- "Davicom 9009", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_0985,
+- "ADMtek Centaur-P", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_ADMTEK, 0x0981,
+- "ADMtek AN981 Comet", 0, 0, 0, 0},
+- { 0x125B, 0x1400,
+- "ASIX AX88140", 0, 0, 0, 0 },
+- { 0x11F6, 0x9881,
+- "Compex RL100-TX", 0, 0, 0, 0 },
+-#endif
+-#ifdef INCLUDE_DAVICOM
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9102,
+- "Davicom 9102", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9009,
+- "Davicom 9009", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_VIA_RHINE
+- { PCI_VENDOR_ID_VIATEC, PCI_DEVICE_ID_VIA_VT6102,
+- "VIA 6102", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_VIATEC, PCI_DEVICE_ID_VIA_RHINE_I,
+- "VIA 3043", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_VIATEC, PCI_DEVICE_ID_VIA_86C100A,
+- "VIA 86C100A", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_W89C840
+- { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C840,
+- "Winbond W89C840F", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_COMPEX, PCI_DEVICE_ID_COMPEX_RL100ATX,
+- "Compex RL100ATX", 0, 0, 0, 0},
+-#endif
+-#ifdef INCLUDE_SIS900
+- { PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS900,
+- "SIS900", 0, 0, 0, 0},
+- { PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS7016,
+- "SIS7016", 0, 0, 0, 0},
+-#endif
+-
+-#ifdef INCLUDE_NATSEMI
+- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_DP83815,
+- "DP83815", 0, 0, 0, 0},
+-#endif
+-
+-#ifdef INCLUDE_TLAN
+- { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2326,
+- "OC2326", 0, 0, 0, 0},
++/*
++ * NIC probing is in pci device order, followed by the
++ * link order of the drivers. A driver that matches
++ * on vendor and device id will supersede a driver
++ * that matches on pci class.
++ *
++ * If you want to probe for another device behind the same pci
++ * device just increment index. And the previous probe call
++ * will be repeated.
++ */
++ struct pci_probe_state *state = &dev->state.pci;
++ printf("Probing pci %s...\n", type_name);
++ if (dev->how_probe == PROBE_FIRST) {
++ state->advance = 1;
++ state->dev.driver = 0;
++ state->dev.bus = 0;
++ state->dev.devfn = 0;
++ dev->index = -1;
++ }
++ for(;;) {
++ if ((dev->how_probe != PROBE_AWAKE) && state->advance) {
++ find_pci(dev->type, &state->dev);
++ dev->index = -1;
++ }
++ state->advance = 1;
++
++ if (state->dev.driver == 0)
++ break;
++
++#if 0
++ /* FIXME the romaddr code needs a total rethought to be useful */
++ if (state->dev.romaddr != ((unsigned long) rom.rom_segment << 4)) {
++ continue;
++ }
++#endif
++ if (dev->how_probe != PROBE_AWAKE) {
++ dev->type_index++;
++ }
++ dev->devid.bus_type = PCI_BUS_TYPE;
++ dev->devid.vendor_id = htons(state->dev.vendor);
++ dev->devid.device_id = htons(state->dev.dev_id);
++ /* FIXME how do I handle dev->index + PROBE_AGAIN?? */
++
++ printf("[%s]", state->dev.name);
++ if (state->dev.driver->probe(dev, &state->dev)) {
++ state->advance = (dev->index == -1);
++ return PROBE_WORKED;
++ }
++ putchar('\n');
++ }
++ return PROBE_FAILED;
++}
+ #endif
+
+- /* other PCI NICs go here */
+- {0, 0, NULL, 0, 0, 0, 0}
+-};
+-#endif /* INCLUDE_*PCI */
+-
+-#include <cards.h>
+-
+-#ifdef INCLUDE_PCI
+-struct pci_dispatch_table
++#ifdef CONFIG_ISA
++static int isa_probe(struct dev *dev, const char *type_name)
+ {
+- unsigned short vendor;
+- unsigned short dev_id;
+- struct nic *(*eth_probe) (struct nic *, unsigned short *,
+- struct pci_device *);
+-};
+-
+-static struct pci_dispatch_table PCI_NIC[] =
+-{
+-# ifdef INCLUDE_NS8390
+- { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8029, nepci_probe },
+- { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940, nepci_probe },
+- { PCI_VENDOR_ID_COMPEX, PCI_DEVICE_ID_COMPEX_RL2000, nepci_probe },
+- { PCI_VENDOR_ID_KTI, PCI_DEVICE_ID_KTI_ET32P2, nepci_probe },
+- { PCI_VENDOR_ID_NETVIN, PCI_DEVICE_ID_NETVIN_NV5000SC, nepci_probe },
+- { PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_HT80232, nepci_probe },
+-# endif /* INCLUDE_NS8390 */
+-# ifdef INCLUDE_3C90X
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900TPO, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900COMBO, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905TX, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905T4, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x9004, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x9005, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x9006, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x900A, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905B_TX, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x9056, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x905A, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C_TXM, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x9800, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x9805, a3c90x_probe },
+- { PCI_VENDOR_ID_3COM, 0x7646, a3c90x_probe },
+-# endif /* INCLUDE_3C90X */
+-# ifdef INCLUDE_3C595
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C590, t595_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C595, t595_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C595_1, t595_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C595_2, t595_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900TPO, t595_probe },
+- { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C900COMBO, t595_probe },
+- { PCI_VENDOR_ID_3COM, 0x9004, t595_probe },
+- { PCI_VENDOR_ID_3COM, 0x9005, t595_probe },
+- { PCI_VENDOR_ID_3COM, 0x9006, t595_probe },
+- { PCI_VENDOR_ID_3COM, 0x900A, t595_probe },
+- { PCI_VENDOR_ID_3COM, 0x9800, t595_probe },
+- { PCI_VENDOR_ID_3COM, 0x9805, t595_probe },
+- { PCI_VENDOR_ID_3COM, 0x7646, t595_probe },
+-# endif /* INCLUDE_3C595 */
+-# ifdef INCLUDE_EEPRO100
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557, eepro100_probe },
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER, eepro100_probe },
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ID1029, eepro100_probe },
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ID1030, eepro100_probe },
+- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82562, eepro100_probe },
+-# endif /* INCLUDE_EEPRO100 */
+-# ifdef INCLUDE_EPIC100
+- { PCI_VENDOR_ID_SMC, PCI_DEVICE_ID_SMC_EPIC100, epic100_probe },
+-# endif /* INCLUDE_EPIC100 */
+-# ifdef INCLUDE_LANCE
+- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, lancepci_probe },
+- { PCI_VENDOR_ID_AMD_HOMEPNA, PCI_DEVICE_ID_AMD_HOMEPNA, lancepci_probe },
+-# endif /* INCLUDE_LANCE */
+-# ifdef INCLUDE_RTL8139
+- { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139, rtl8139_probe },
+- { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DFE530TXP, rtl8139_probe },
+- { PCI_VENDOR_ID_SMC_1211, PCI_DEVICE_ID_SMC_1211, rtl8139_probe },
+-# endif /* INCLUDE_RTL8139 */
+-# ifdef INCLUDE_OTULIP
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP, otulip_probe },
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST, otulip_probe },
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS, otulip_probe },
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, otulip_probe },
+-# endif /* INCLUDE_OTULIP */
+-# ifdef INCLUDE_TULIP
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP, tulip_probe },
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST, tulip_probe },
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS, tulip_probe },
+- { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, tulip_probe },
+- { PCI_VENDOR_ID_MACRONIX, PCI_DEVICE_ID_MX987x5, tulip_probe },
+- { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LC82C115, tulip_probe },
+- { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_DEC_TULIP, tulip_probe },
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9102, tulip_probe },
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9009, tulip_probe },
+- { PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_0985, tulip_probe },
+- { PCI_VENDOR_ID_ADMTEK, 0x0981, tulip_probe },
+- { 0x125B, 0x1400, tulip_probe },
+- { 0x11F6, 0x9881, tulip_probe },
+-# endif /* INCLUDE_TULIP */
+-# ifdef INCLUDE_DAVICOM
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9102, davicom_probe },
+- { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DM9009, davicom_probe },
+-# endif /* INCLUDE_DAVICOM */
+-# ifdef INCLUDE_VIA_RHINE
+- { PCI_VENDOR_ID_VIATEC, PCI_DEVICE_ID_VIA_VT6102, rhine_probe },
+- { PCI_VENDOR_ID_VIATEC, PCI_DEVICE_ID_VIA_RHINE_I, rhine_probe },
+- { PCI_VENDOR_ID_VIATEC, PCI_DEVICE_ID_VIA_86C100A, rhine_probe },
+-# endif /* INCLUDE_VIA_RHINE */
+-# ifdef INCLUDE_W89C840
+- { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C840, w89c840_probe },
+- { PCI_VENDOR_ID_COMPEX, PCI_DEVICE_ID_COMPEX_RL100ATX, w89c840_probe },
+-# endif /* INCLUDE_W89C840 */
+-# ifdef INCLUDE_SIS900
+- { PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS900, sis900_probe },
+- { PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS7016, sis900_probe },
+-# endif /* INCLUDE_SIS900 */
+-# ifdef INCLUDE_NATSEMI
+- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_DP83815, natsemi_probe },
+-# endif /* INCLUDE_NATSEMI */
+-# ifdef INCLUDE_TLAN
+- { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2326, tlan_probe },
+-# endif /* INCLUDE_TLAN */
+- { 0, 0, 0 }
+-};
+-#endif /* GRUB && INCLUDE_PCI */
+-
+-struct dispatch_table
+-{
+- const char *nic_name;
+-#ifdef INCLUDE_PCI
+- struct nic *(*eth_probe) (struct nic *, unsigned short *,
+- struct pci_device *);
+-#else
+- struct nic *(*eth_probe) (struct nic *, unsigned short *);
+-#endif /* INCLUDE_PCI */
+- unsigned short *probe_ioaddrs; /* for probe overrides */
+-};
+-
+ /*
+- * NIC probing is in order of appearance in this table.
++ * NIC probing is in the order the drivers were linked togeter.
+ * If for some reason you want to change the order,
+- * just rearrange the entries (bracketed by the #ifdef/#endif)
++ * just change the order you list the drivers in.
+ */
+-static struct dispatch_table NIC[] =
+-{
+-#ifdef INCLUDE_RTL8139
+- { "RTL8139", rtl8139_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_SIS900
+- { "SIS900", sis900_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_NATSEMI
+- { "NATSEMI", natsemi_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_WD
+- { "WD", wd_probe, 0 },
+-#endif
+-#ifdef INCLUDE_3C503
+- { "3C503", t503_probe, 0 },
+-#endif
+-#ifdef INCLUDE_NE
+- { "NE*000", ne_probe, 0 },
+-#endif
+-#ifdef INCLUDE_3C509
+- { "3C5x9", t509_probe, 0 },
+-#endif
+-#ifdef INCLUDE_3C529
+- { "3C5x9", t529_probe, 0 },
+-#endif
+-#ifdef INCLUDE_3C595
+- { "3C595", t595_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_3C90X
+- { "3C90X", a3c90x_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_EEPRO
+- { "EEPRO", eepro_probe, 0 },
+-#endif
+-#ifdef INCLUDE_EEPRO100
+- { "EEPRO100", eepro100_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_EPIC100
+- { "EPIC100", epic100_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_OTULIP
+- { "OTulip", otulip_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_TULIP
+- { "Tulip", tulip_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_DAVICOM
+- { "DAVICOM", davicom_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_CS89X0
+- { "CS89x0", cs89x0_probe, 0 },
+-#endif
+-#ifdef INCLUDE_NE2100
+- { "NE2100", ne2100_probe, 0 },
+-#endif
+-#ifdef INCLUDE_NI6510
+- { "NI6510", ni6510_probe, 0 },
+-#endif
+-#ifdef INCLUDE_SK_G16
+- { "SK_G16", SK_probe, 0 },
+-#endif
+-#ifdef INCLUDE_3C507
+- { "3C507", t507_probe, 0 },
+-#endif
+-#ifdef INCLUDE_NI5010
+- { "NI5010", ni5010_probe, 0 },
+-#endif
+-#ifdef INCLUDE_NI5210
+- { "NI5210", ni5210_probe, 0 },
+-#endif
+-#ifdef INCLUDE_EXOS205
+- { "EXOS205", exos205_probe, 0 },
+-#endif
+-#ifdef INCLUDE_SMC9000
+- { "SMC9000", smc9000_probe, 0 },
+-#endif
+-#ifdef INCLUDE_TIARA
+- { "TIARA", tiara_probe, 0 },
+-#endif
+-#ifdef INCLUDE_DEPCA
+- { "DEPCA", depca_probe, 0 },
+-#endif
+-#ifdef INCLUDE_NS8390
+- { "NE2000/PCI", nepci_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_LANCE
+- { "LANCE/PCI", lancepci_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_VIA_RHINE
+- { "VIA 86C100", rhine_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_W89C840
+- { "W89C840F", w89c840_probe, pci_ioaddrs },
+-#endif
+-#ifdef INCLUDE_TLAN
+- { "Olicom 2326", tlan_probe, pci_ioaddrs },
+-#endif
+- /* this entry must always be last to mark the end of list */
+- { 0, 0, 0 }
+-};
+-
+-#define NIC_TABLE_SIZE (sizeof (NIC) / sizeof (NIC[0]))
+-
+-static int
+-eth_dummy (struct nic *dummy)
+-{
+- return 0;
++ struct isa_probe_state *state = &dev->state.isa;
++ printf("Probing isa %s...\n", type_name);
++ if (dev->how_probe == PROBE_FIRST) {
++ state->advance = 0;
++ state->driver = isa_drivers;
++ dev->index = -1;
++ }
++ for(;;)
++ {
++ if ((dev->how_probe != PROBE_AWAKE) && state->advance) {
++ state->driver++;
++ dev->index = -1;
++ }
++ state->advance = 1;
++
++ if (state->driver >= isa_drivers_end)
++ break;
++
++ if (state->driver->type != dev->type)
++ continue;
++
++ if (dev->how_probe != PROBE_AWAKE) {
++ dev->type_index++;
++ }
++ printf("[%s]", state->driver->name);
++ dev->devid.bus_type = ISA_BUS_TYPE;
++ /* FIXME how do I handle dev->index + PROBE_AGAIN?? */
++ /* driver will fill in vendor and device IDs */
++ if (state->driver->probe(dev, state->driver->ioaddrs)) {
++ state->advance = (dev->index == -1);
++ return PROBE_WORKED;
++ }
++ putchar('\n');
++ }
++ return PROBE_FAILED;
+ }
+-
+-static char packet[ETH_FRAME_LEN];
+-
+-struct nic nic =
+-{
+- (void (*) (struct nic *)) eth_dummy, /* reset */
+- eth_dummy, /* poll */
+- (void (*) (struct nic *, const char *,
+- unsigned int, unsigned int,
+- const char *)) eth_dummy, /* transmit */
+- (void (*) (struct nic *)) eth_dummy, /* disable */
+-#ifdef T503_AUI
+- 1, /* aui */
+ #else
+- 0, /* no aui */
++#define isa_probe(d,tn) (PROBE_FAILED)
+ #endif
+- &rom, /* rom_info */
+- arptable[ARP_CLIENT].node, /* node_addr */
+- packet, /* packet */
+- 0, /* packetlen */
+- 0, /* priv_data */
++static const char *driver_name[] = {
++ "nic",
++ "disk",
++ "floppy",
+ };
+-
+-void
+-eth_reset (void)
++int probe(struct dev *dev)
+ {
+- (*nic.reset) (&nic);
+-}
++ const char *type_name;
+
+-int
+-eth_probe (void)
+-{
+- struct pci_device *p;
+- const struct dispatch_table *t;
+- static int probed = 0;
++ EnterFunction("probe");
+
+- /* If already probed, don't try to probe it any longer. */
+- if (probed)
+- return 1;
+-
+- /* Clear the ready flag. */
+- network_ready = 0;
+- /* Clear the ARP table. */
+- grub_memset ((char *) arptable, 0,
+- MAX_ARP * sizeof (struct arptable_t));
+-
+- p = 0;
+-
+-#ifdef INCLUDE_PCI
+- /* In GRUB, the ROM info is initialized here. */
+- rom = *((struct rom_info *) ROM_INFO_LOCATION);
+-
+- eth_pci_init(pci_nic_list);
+- pci_ioaddrs[0] = 0;
+- pci_ioaddrs[1] = 0;
+- /* at this point we have a list of possible PCI candidates
+- we just pick the first one with a non-zero ioaddr */
+- for (p = pci_nic_list; p->vendor != 0; ++p)
+- {
+- if (p->ioaddr != 0)
+- {
+- pci_ioaddrs[0] = p->ioaddr;
+- break;
++ type_name = "";
++ if ((dev->type >= 0) &&
++ (dev->type < sizeof(driver_name)/sizeof(driver_name[0]))) {
++ type_name = driver_name[dev->type];
+ }
+- }
+-#endif
+-
+- etherboot_printf("Probing...");
+-
+-#ifdef INCLUDE_PCI
+- if (p->vendor)
+- {
+- struct pci_dispatch_table *pt;
+-
+- for (pt = PCI_NIC; pt->eth_probe != 0; pt++)
+- if (p->vendor == pt->vendor && p->dev_id == pt->dev_id)
+- {
+- etherboot_printf ("[%s]", p->name);
+- if ((pt->eth_probe) (&nic, pci_ioaddrs, p))
+- {
+- probed = 1;
+- return 1;
+- }
+- }
+- }
+-#endif /* INCLUDE_PCI */
+-
+- for (t = NIC; t->nic_name != 0; ++t)
+- {
+- etherboot_printf("[%s]", t->nic_name);
+-#ifdef INCLUDE_PCI
+- if ((*t->eth_probe) (&nic, t->probe_ioaddrs, p))
+- {
+- probed = 1;
+- return 1;
++ if (dev->how_probe == PROBE_FIRST) {
++ dev->to_probe = PROBE_PCI;
++ memset(&dev->state, 0, sizeof(dev->state));
+ }
+-#else
+- if ((*t->eth_probe) (&nic, t->probe_ioaddrs))
+- {
+- probed = 1;
+- return 1;
++ if (dev->to_probe == PROBE_PCI) {
++ dev->how_probe = pci_probe(dev, type_name);
++ if (dev->how_probe == PROBE_FAILED) {
++ dev->to_probe = PROBE_ISA;
++ }
++ }
++ if (dev->to_probe == PROBE_ISA) {
++ dev->how_probe = isa_probe(dev, type_name);
++ if (dev->how_probe == PROBE_FAILED) {
++ dev->to_probe = PROBE_NONE;
++ }
++ }
++ if ((dev->to_probe != PROBE_PCI) &&
++ (dev->to_probe != PROBE_ISA)) {
++ dev->how_probe = PROBE_FAILED;
++
+ }
+-#endif /* INCLUDE_PCI */
+- }
+-
+- return 0;
+-}
+-
+-int
+-eth_poll (void)
+-{
+- return ((*nic.poll) (&nic));
+-}
+
+-void
+-eth_transmit (const char *d, unsigned int t, unsigned int s, const void *p)
+-{
+- (*nic.transmit) (&nic, d, t, s, p);
+- if (t == IP)
+- twiddle ();
++ LeaveFunction("probe");
++ return dev->how_probe;
+ }
+
+-void
+-eth_disable (void)
++void disable(struct dev *dev)
+ {
+- (*nic.disable) (&nic);
++ if (dev->disable) {
++ dev->disable(dev);
++ dev->disable = 0;
++ }
+ }
+diff -Naur grub-0.97.orig/netboot/cpu.h grub-0.97/netboot/cpu.h
+--- grub-0.97.orig/netboot/cpu.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/cpu.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,243 @@
++#ifndef I386_BITS_CPU_H
++#define I386_BITS_CPU_H
++
++
++/* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
++#define CPU_FEATURE_P(CAP, FEATURE) \
++ (!!(CAP[(X86_FEATURE_##FEATURE)/32] & ((X86_FEATURE_##FEATURE) & 0x1f)))
++
++#define NCAPINTS 4 /* Currently we have 4 32-bit words worth of info */
++
++/* Intel-defined CPU features, CPUID level 0x00000001, word 0 */
++#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
++#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
++#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
++#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
++#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
++#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
++#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
++#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
++#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
++#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
++#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
++#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
++#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
++#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
++#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
++#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
++#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
++#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
++#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
++#define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */
++#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
++#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
++#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
++ /* of FPU context), and CR4.OSFXSR available */
++#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
++#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
++#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
++#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
++#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
++#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
++
++/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
++/* Don't duplicate feature flags which are redundant with Intel! */
++#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
++#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
++#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
++#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
++#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
++
++/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
++#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
++#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
++#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
++
++/* Other features, Linux-defined mapping, word 3 */
++/* This range is used for feature bits which conflict or are synthesized */
++#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
++#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
++#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
++#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
++
++#define MAX_X86_VENDOR_ID 16
++struct cpuinfo_x86 {
++ uint8_t x86; /* CPU family */
++ uint8_t x86_model;
++ uint8_t x86_mask;
++
++ int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
++ unsigned x86_capability[NCAPINTS];
++ char x86_vendor_id[MAX_X86_VENDOR_ID];
++};
++
++
++#define X86_VENDOR_INTEL 0
++#define X86_VENDOR_CYRIX 1
++#define X86_VENDOR_AMD 2
++#define X86_VENDOR_UMC 3
++#define X86_VENDOR_NEXGEN 4
++#define X86_VENDOR_CENTAUR 5
++#define X86_VENDOR_RISE 6
++#define X86_VENDOR_TRANSMETA 7
++#define X86_VENDOR_NSC 8
++#define X86_VENDOR_UNKNOWN 0xff
++
++/*
++ * EFLAGS bits
++ */
++#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
++#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
++#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
++#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
++#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
++#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
++#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
++#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
++#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
++#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
++#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
++#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
++#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
++#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
++#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
++#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
++#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
++
++/*
++ * Generic CPUID function
++ */
++static inline void cpuid(int op,
++ unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
++{
++ __asm__("cpuid"
++ : "=a" (*eax),
++ "=b" (*ebx),
++ "=c" (*ecx),
++ "=d" (*edx)
++ : "0" (op));
++}
++
++/*
++ * CPUID functions returning a single datum
++ */
++static inline unsigned int cpuid_eax(unsigned int op)
++{
++ unsigned int eax;
++
++ __asm__("cpuid"
++ : "=a" (eax)
++ : "0" (op)
++ : "bx", "cx", "dx");
++ return eax;
++}
++static inline unsigned int cpuid_ebx(unsigned int op)
++{
++ unsigned int eax, ebx;
++
++ __asm__("cpuid"
++ : "=a" (eax), "=b" (ebx)
++ : "0" (op)
++ : "cx", "dx" );
++ return ebx;
++}
++static inline unsigned int cpuid_ecx(unsigned int op)
++{
++ unsigned int eax, ecx;
++
++ __asm__("cpuid"
++ : "=a" (eax), "=c" (ecx)
++ : "0" (op)
++ : "bx", "dx" );
++ return ecx;
++}
++static inline unsigned int cpuid_edx(unsigned int op)
++{
++ unsigned int eax, edx;
++
++ __asm__("cpuid"
++ : "=a" (eax), "=d" (edx)
++ : "0" (op)
++ : "bx", "cx");
++ return edx;
++}
++
++/*
++ * Intel CPU features in CR4
++ */
++#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
++#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
++#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
++#define X86_CR4_DE 0x0008 /* enable debugging extensions */
++#define X86_CR4_PSE 0x0010 /* enable page size extensions */
++#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
++#define X86_CR4_MCE 0x0040 /* Machine check enable */
++#define X86_CR4_PGE 0x0080 /* enable global pages */
++#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
++#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
++#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
++
++
++#define MSR_K6_EFER 0xC0000080
++/* EFER bits: */
++#define _EFER_SCE 0 /* SYSCALL/SYSRET */
++#define _EFER_LME 8 /* Long mode enable */
++#define _EFER_LMA 10 /* Long mode active (read-only) */
++#define _EFER_NX 11 /* No execute enable */
++
++#define EFER_SCE (1<<_EFER_SCE)
++#define EFER_LME (1<<EFER_LME)
++#define EFER_LMA (1<<EFER_LMA)
++#define EFER_NX (1<<_EFER_NX)
++
++#define rdmsr(msr,val1,val2) \
++ __asm__ __volatile__("rdmsr" \
++ : "=a" (val1), "=d" (val2) \
++ : "c" (msr))
++
++#define wrmsr(msr,val1,val2) \
++ __asm__ __volatile__("wrmsr" \
++ : /* no outputs */ \
++ : "c" (msr), "a" (val1), "d" (val2))
++
++
++#define read_cr0() ({ \
++ unsigned int __dummy; \
++ __asm__( \
++ "movl %%cr0, %0\n\t" \
++ :"=r" (__dummy)); \
++ __dummy; \
++})
++#define write_cr0(x) \
++ __asm__("movl %0,%%cr0": :"r" (x));
++
++#define read_cr3() ({ \
++ unsigned int __dummy; \
++ __asm__( \
++ "movl %%cr3, %0\n\t" \
++ :"=r" (__dummy)); \
++ __dummy; \
++})
++#define write_cr3x(x) \
++ __asm__("movl %0,%%cr3": :"r" (x));
++
++
++#define read_cr4() ({ \
++ unsigned int __dummy; \
++ __asm__( \
++ "movl %%cr4, %0\n\t" \
++ :"=r" (__dummy)); \
++ __dummy; \
++})
++#define write_cr4x(x) \
++ __asm__("movl %0,%%cr4": :"r" (x));
++
++
++extern struct cpuinfo_x86 cpu_info;
++#ifdef CONFIG_X86_64
++extern void cpu_setup(void);
++#else
++#define cpu_setup() do {} while(0)
++#endif
++
++#endif /* I386_BITS_CPU_H */
+diff -Naur grub-0.97.orig/netboot/cs89x0.c grub-0.97/netboot/cs89x0.c
+--- grub-0.97.orig/netboot/cs89x0.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/cs89x0.c 1970-01-01 00:00:00.000000000 +0000
+@@ -1,659 +0,0 @@
+-/* cs89x0.c: A Crystal Semiconductor CS89[02]0 driver for etherboot. */
+-/*
+- Permission is granted to distribute the enclosed cs89x0.[ch] driver
+- only in conjunction with the Etherboot package. The code is
+- ordinarily distributed under the GPL.
+-
+- Russ Nelson, January 2000
+-
+- ChangeLog:
+-
+- Thu Dec 6 22:40:00 1996 Markus Gutschke <gutschk@math.uni-muenster.de>
+-
+- * disabled all "advanced" features; this should make the code more reliable
+-
+- * reorganized the reset function
+-
+- * always reset the address port, so that autoprobing will continue working
+-
+- * some cosmetic changes
+-
+- * 2.5
+-
+- Thu Dec 5 21:00:00 1996 Markus Gutschke <gutschk@math.uni-muenster.de>
+-
+- * tested the code against a CS8900 card
+-
+- * lots of minor bug fixes and adjustments
+-
+- * this is the first release, that actually works! it still requires some
+- changes in order to be more tolerant to different environments
+-
+- * 4
+-
+- Fri Nov 22 23:00:00 1996 Markus Gutschke <gutschk@math.uni-muenster.de>
+-
+- * read the manuals for the CS89x0 chipsets and took note of all the
+- changes that will be neccessary in order to adapt Russel Nelson's code
+- to the requirements of a BOOT-Prom
+-
+- * 6
+-
+- Thu Nov 19 22:00:00 1996 Markus Gutschke <gutschk@math.uni-muenster.de>
+-
+- * Synched with Russel Nelson's current code (v1.00)
+-
+- * 2
+-
+- Thu Nov 12 18:00:00 1996 Markus Gutschke <gutschk@math.uni-muenster.de>
+-
+- * Cleaned up some of the code and tried to optimize the code size.
+-
+- * 1.5
+-
+- Sun Nov 10 16:30:00 1996 Markus Gutschke <gutschk@math.uni-muenster.de>
+-
+- * First experimental release. This code compiles fine, but I
+- have no way of testing whether it actually works.
+-
+- * I did not (yet) bother to make the code 16bit aware, so for
+- the time being, it will only work for Etherboot/32.
+-
+- * 12
+-
+- */
+-
+-#include "etherboot.h"
+-#include "nic.h"
+-#include "cards.h"
+-#include "cs89x0.h"
+-
+-static unsigned short eth_nic_base;
+-static unsigned long eth_mem_start;
+-static unsigned short eth_irq;
+-static unsigned short eth_cs_type; /* one of: CS8900, CS8920, CS8920M */
+-static unsigned short eth_auto_neg_cnf;
+-static unsigned short eth_adapter_cnf;
+-static unsigned short eth_linectl;
+-
+-/*************************************************************************
+- CS89x0 - specific routines
+-**************************************************************************/
+-
+-static inline int readreg(int portno)
+-{
+- outw(portno, eth_nic_base + ADD_PORT);
+- return inw(eth_nic_base + DATA_PORT);
+-}
+-
+-static inline void writereg(int portno, int value)
+-{
+- outw(portno, eth_nic_base + ADD_PORT);
+- outw(value, eth_nic_base + DATA_PORT);
+- return;
+-}
+-
+-/*************************************************************************
+-EEPROM access
+-**************************************************************************/
+-
+-static int wait_eeprom_ready(void)
+-{
+- unsigned long tmo = currticks() + 4*TICKS_PER_SEC;
+-
+- /* check to see if the EEPROM is ready, a timeout is used -
+- just in case EEPROM is ready when SI_BUSY in the
+- PP_SelfST is clear */
+- while(readreg(PP_SelfST) & SI_BUSY) {
+- if (currticks() >= tmo)
+- return -1; }
+- return 0;
+-}
+-
+-static int get_eeprom_data(int off, int len, unsigned short *buffer)
+-{
+- int i;
+-
+-#ifdef EDEBUG
+- printf("\ncs: EEPROM data from %hX for %hX:",off,len);
+-#endif
+- for (i = 0; i < len; i++) {
+- if (wait_eeprom_ready() < 0)
+- return -1;
+- /* Now send the EEPROM read command and EEPROM location
+- to read */
+- writereg(PP_EECMD, (off + i) | EEPROM_READ_CMD);
+- if (wait_eeprom_ready() < 0)
+- return -1;
+- buffer[i] = readreg(PP_EEData);
+-#ifdef EDEBUG
+- if (!(i%10))
+- printf("\ncs: ");
+- printf("%hX ", buffer[i]);
+-#endif
+- }
+-#ifdef EDEBUG
+- putchar('\n');
+-#endif
+-
+- return(0);
+-}
+-
+-static int get_eeprom_chksum(int off, int len, unsigned short *buffer)
+-{
+- int i, cksum;
+-
+- cksum = 0;
+- for (i = 0; i < len; i++)
+- cksum += buffer[i];
+- cksum &= 0xffff;
+- if (cksum == 0)
+- return 0;
+- return -1;
+-}
+-
+-/*************************************************************************
+-Activate all of the available media and probe for network
+-**************************************************************************/
+-
+-static void clrline(void)
+-{
+- int i;
+-
+- putchar('\r');
+- for (i = 79; i--; ) putchar(' ');
+- printf("\rcs: ");
+- return;
+-}
+-
+-static void control_dc_dc(int on_not_off)
+-{
+- unsigned int selfcontrol;
+- unsigned long tmo = currticks() + TICKS_PER_SEC;
+-
+- /* control the DC to DC convertor in the SelfControl register. */
+- selfcontrol = HCB1_ENBL; /* Enable the HCB1 bit as an output */
+- if (((eth_adapter_cnf & A_CNF_DC_DC_POLARITY) != 0) ^ on_not_off)
+- selfcontrol |= HCB1;
+- else
+- selfcontrol &= ~HCB1;
+- writereg(PP_SelfCTL, selfcontrol);
+-
+- /* Wait for the DC/DC converter to power up - 1000ms */
+- while (currticks() < tmo);
+-
+- return;
+-}
+-
+-static int detect_tp(void)
+-{
+- unsigned long tmo;
+-
+- /* Turn on the chip auto detection of 10BT/ AUI */
+-
+- clrline(); printf("attempting %s:","TP");
+-
+- /* If connected to another full duplex capable 10-Base-T card
+- the link pulses seem to be lost when the auto detect bit in
+- the LineCTL is set. To overcome this the auto detect bit
+- will be cleared whilst testing the 10-Base-T interface.
+- This would not be necessary for the sparrow chip but is
+- simpler to do it anyway. */
+- writereg(PP_LineCTL, eth_linectl &~ AUI_ONLY);
+- control_dc_dc(0);
+-
+- /* Delay for the hardware to work out if the TP cable is
+- present - 150ms */
+- for (tmo = currticks() + 4; currticks() < tmo; );
+-
+- if ((readreg(PP_LineST) & LINK_OK) == 0)
+- return 0;
+-
+- if (eth_cs_type != CS8900) {
+-
+- writereg(PP_AutoNegCTL, eth_auto_neg_cnf & AUTO_NEG_MASK);
+-
+- if ((eth_auto_neg_cnf & AUTO_NEG_BITS) == AUTO_NEG_ENABLE) {
+- printf(" negotiating duplex... ");
+- while (readreg(PP_AutoNegST) & AUTO_NEG_BUSY) {
+- if (currticks() - tmo > 40*TICKS_PER_SEC) {
+- printf("time out ");
+- break;
+- }
+- }
+- }
+- if (readreg(PP_AutoNegST) & FDX_ACTIVE)
+- printf("using full duplex");
+- else
+- printf("using half duplex");
+- }
+-
+- return A_CNF_MEDIA_10B_T;
+-}
+-
+-/* send a test packet - return true if carrier bits are ok */
+-static int send_test_pkt(struct nic *nic)
+-{
+- static unsigned char testpacket[] = { 0,0,0,0,0,0, 0,0,0,0,0,0,
+- 0, 46, /*A 46 in network order */
+- 0, 0, /*DSAP=0 & SSAP=0 fields */
+- 0xf3,0 /*Control (Test Req+P bit set)*/ };
+- unsigned long tmo;
+-
+- writereg(PP_LineCTL, readreg(PP_LineCTL) | SERIAL_TX_ON);
+-
+- memcpy(testpacket, nic->node_addr, ETH_ALEN);
+- memcpy(testpacket+ETH_ALEN, nic->node_addr, ETH_ALEN);
+-
+- outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT);
+- outw(ETH_ZLEN, eth_nic_base + TX_LEN_PORT);
+-
+- /* Test to see if the chip has allocated memory for the packet */
+- for (tmo = currticks() + 2;
+- (readreg(PP_BusST) & READY_FOR_TX_NOW) == 0; )
+- if (currticks() >= tmo)
+- return(0);
+-
+- /* Write the contents of the packet */
+- outsw(eth_nic_base + TX_FRAME_PORT, testpacket,
+- (ETH_ZLEN+1)>>1);
+-
+- printf(" sending test packet ");
+- /* wait a couple of timer ticks for packet to be received */
+- for (tmo = currticks() + 2; currticks() < tmo; );
+-
+- if ((readreg(PP_TxEvent) & TX_SEND_OK_BITS) == TX_OK) {
+- printf("succeeded");
+- return 1;
+- }
+- printf("failed");
+- return 0;
+-}
+-
+-
+-static int detect_aui(struct nic *nic)
+-{
+- clrline(); printf("attempting %s:","AUI");
+- control_dc_dc(0);
+-
+- writereg(PP_LineCTL, (eth_linectl & ~AUTO_AUI_10BASET) | AUI_ONLY);
+-
+- if (send_test_pkt(nic)) {
+- return A_CNF_MEDIA_AUI; }
+- else
+- return 0;
+-}
+-
+-static int detect_bnc(struct nic *nic)
+-{
+- clrline(); printf("attempting %s:","BNC");
+- control_dc_dc(1);
+-
+- writereg(PP_LineCTL, (eth_linectl & ~AUTO_AUI_10BASET) | AUI_ONLY);
+-
+- if (send_test_pkt(nic)) {
+- return A_CNF_MEDIA_10B_2; }
+- else
+- return 0;
+-}
+-
+-/**************************************************************************
+-ETH_RESET - Reset adapter
+-***************************************************************************/
+-
+-static void cs89x0_reset(struct nic *nic)
+-{
+- int i;
+- unsigned long reset_tmo;
+-
+- writereg(PP_SelfCTL, readreg(PP_SelfCTL) | POWER_ON_RESET);
+-
+- /* wait for two ticks; that is 2*55ms */
+- for (reset_tmo = currticks() + 2; currticks() < reset_tmo; );
+-
+- if (eth_cs_type != CS8900) {
+- /* Hardware problem requires PNP registers to be reconfigured
+- after a reset */
+- if (eth_irq != 0xFFFF) {
+- outw(PP_CS8920_ISAINT, eth_nic_base + ADD_PORT);
+- outb(eth_irq, eth_nic_base + DATA_PORT);
+- outb(0, eth_nic_base + DATA_PORT + 1); }
+-
+- if (eth_mem_start) {
+- outw(PP_CS8920_ISAMemB, eth_nic_base + ADD_PORT);
+- outb((eth_mem_start >> 8) & 0xff, eth_nic_base + DATA_PORT);
+- outb((eth_mem_start >> 24) & 0xff, eth_nic_base + DATA_PORT + 1); } }
+-
+- /* Wait until the chip is reset */
+- for (reset_tmo = currticks() + 2;
+- (readreg(PP_SelfST) & INIT_DONE) == 0 &&
+- currticks() < reset_tmo; );
+-
+- /* disable interrupts and memory accesses */
+- writereg(PP_BusCTL, 0);
+-
+- /* set the ethernet address */
+- for (i=0; i < ETH_ALEN/2; i++)
+- writereg(PP_IA+i*2,
+- nic->node_addr[i*2] |
+- (nic->node_addr[i*2+1] << 8));
+-
+- /* receive only error free packets addressed to this card */
+- writereg(PP_RxCTL, DEF_RX_ACCEPT);
+-
+- /* do not generate any interrupts on receive operations */
+- writereg(PP_RxCFG, 0);
+-
+- /* do not generate any interrupts on transmit operations */
+- writereg(PP_TxCFG, 0);
+-
+- /* do not generate any interrupts on buffer operations */
+- writereg(PP_BufCFG, 0);
+-
+- /* reset address port, so that autoprobing will keep working */
+- outw(PP_ChipID, eth_nic_base + ADD_PORT);
+-
+- return;
+-}
+-
+-/**************************************************************************
+-ETH_TRANSMIT - Transmit a frame
+-***************************************************************************/
+-
+-static void cs89x0_transmit(
+- struct nic *nic,
+- const char *d, /* Destination */
+- unsigned int t, /* Type */
+- unsigned int s, /* size */
+- const char *p) /* Packet */
+-{
+- unsigned long tmo;
+- int sr;
+-
+- /* does this size have to be rounded??? please,
+- somebody have a look in the specs */
+- if ((sr = ((s + ETH_HLEN + 1)&~1)) < ETH_ZLEN)
+- sr = ETH_ZLEN;
+-
+-retry:
+- /* initiate a transmit sequence */
+- outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT);
+- outw(sr, eth_nic_base + TX_LEN_PORT);
+-
+- /* Test to see if the chip has allocated memory for the packet */
+- if ((readreg(PP_BusST) & READY_FOR_TX_NOW) == 0) {
+- /* Oops... this should not happen! */
+- printf("cs: unable to send packet; retrying...\n");
+- for (tmo = currticks() + 5*TICKS_PER_SEC; currticks() < tmo; );
+- cs89x0_reset(nic);
+- goto retry; }
+-
+- /* Write the contents of the packet */
+- outsw(eth_nic_base + TX_FRAME_PORT, d, ETH_ALEN/2);
+- outsw(eth_nic_base + TX_FRAME_PORT, nic->node_addr,
+- ETH_ALEN/2);
+- outw(((t >> 8)&0xFF)|(t << 8), eth_nic_base + TX_FRAME_PORT);
+- outsw(eth_nic_base + TX_FRAME_PORT, p, (s+1)/2);
+- for (sr = sr/2 - (s+1)/2 - ETH_ALEN - 1; sr-- > 0;
+- outw(0, eth_nic_base + TX_FRAME_PORT));
+-
+- /* wait for transfer to succeed */
+- for (tmo = currticks()+5*TICKS_PER_SEC;
+- (s = readreg(PP_TxEvent)&~0x1F) == 0 && currticks() < tmo;)
+- /* nothing */ ;
+- if ((s & TX_SEND_OK_BITS) != TX_OK) {
+- printf("\ntransmission error %#hX\n", s);
+- }
+-
+- return;
+-}
+-
+-/**************************************************************************
+-ETH_POLL - Wait for a frame
+-***************************************************************************/
+-
+-static int cs89x0_poll(struct nic *nic)
+-{
+- int status;
+-
+- status = readreg(PP_RxEvent);
+-
+- if ((status & RX_OK) == 0)
+- return(0);
+-
+- status = inw(eth_nic_base + RX_FRAME_PORT);
+- nic->packetlen = inw(eth_nic_base + RX_FRAME_PORT);
+- insw(eth_nic_base + RX_FRAME_PORT, nic->packet, nic->packetlen >> 1);
+- if (nic->packetlen & 1)
+- nic->packet[nic->packetlen-1] = inw(eth_nic_base + RX_FRAME_PORT);
+- return 1;
+-}
+-
+-static void cs89x0_disable(struct nic *nic)
+-{
+- cs89x0_reset(nic);
+-}
+-
+-/**************************************************************************
+-ETH_PROBE - Look for an adapter
+-***************************************************************************/
+-
+-struct nic *cs89x0_probe(struct nic *nic, unsigned short *probe_addrs)
+-{
+- static const unsigned int netcard_portlist[] = {
+-#ifdef CS_SCAN
+- CS_SCAN,
+-#else /* use "conservative" default values for autoprobing */
+- 0x300,0x320,0x340,0x200,0x220,0x240,
+- 0x260,0x280,0x2a0,0x2c0,0x2e0,
+- /* if that did not work, then be more aggressive */
+- 0x301,0x321,0x341,0x201,0x221,0x241,
+- 0x261,0x281,0x2a1,0x2c1,0x2e1,
+-#endif
+- 0};
+-
+- int i, result = -1;
+- unsigned rev_type = 0, ioaddr, ioidx, isa_cnf, cs_revision;
+- unsigned short eeprom_buff[CHKSUM_LEN];
+-
+-
+- for (ioidx = 0; (ioaddr=netcard_portlist[ioidx++]) != 0; ) {
+- /* if they give us an odd I/O address, then do ONE write to
+- the address port, to get it back to address zero, where we
+- expect to find the EISA signature word. */
+- if (ioaddr & 1) {
+- ioaddr &= ~1;
+- if ((inw(ioaddr + ADD_PORT) & ADD_MASK) != ADD_SIG)
+- continue;
+- outw(PP_ChipID, ioaddr + ADD_PORT);
+- }
+-
+- if (inw(ioaddr + DATA_PORT) != CHIP_EISA_ID_SIG)
+- continue;
+- eth_nic_base = ioaddr;
+-
+- /* get the chip type */
+- rev_type = readreg(PRODUCT_ID_ADD);
+- eth_cs_type = rev_type &~ REVISON_BITS;
+- cs_revision = ((rev_type & REVISON_BITS) >> 8) + 'A';
+-
+- printf("\ncs: cs89%c0%s rev %c, base %#hX",
+- eth_cs_type==CS8900?'0':'2',
+- eth_cs_type==CS8920M?"M":"",
+- cs_revision,
+- eth_nic_base);
+-
+- /* First check to see if an EEPROM is attached*/
+- if ((readreg(PP_SelfST) & EEPROM_PRESENT) == 0) {
+- printf("\ncs: no EEPROM...\n");
+- outw(PP_ChipID, eth_nic_base + ADD_PORT);
+- continue; }
+- else if (get_eeprom_data(START_EEPROM_DATA,CHKSUM_LEN,
+- eeprom_buff) < 0) {
+- printf("\ncs: EEPROM read failed...\n");
+- outw(PP_ChipID, eth_nic_base + ADD_PORT);
+- continue; }
+- else if (get_eeprom_chksum(START_EEPROM_DATA,CHKSUM_LEN,
+- eeprom_buff) < 0) {
+- printf("\ncs: EEPROM checksum bad...\n");
+- outw(PP_ChipID, eth_nic_base + ADD_PORT);
+- continue; }
+-
+- /* get transmission control word but keep the
+- autonegotiation bits */
+- eth_auto_neg_cnf = eeprom_buff[AUTO_NEG_CNF_OFFSET/2];
+- /* Store adapter configuration */
+- eth_adapter_cnf = eeprom_buff[ADAPTER_CNF_OFFSET/2];
+- /* Store ISA configuration */
+- isa_cnf = eeprom_buff[ISA_CNF_OFFSET/2];
+-
+- /* store the initial memory base address */
+- eth_mem_start = eeprom_buff[PACKET_PAGE_OFFSET/2] << 8;
+-
+- printf("%s%s%s, addr ",
+- (eth_adapter_cnf & A_CNF_10B_T)?", RJ-45":"",
+- (eth_adapter_cnf & A_CNF_AUI)?", AUI":"",
+- (eth_adapter_cnf & A_CNF_10B_2)?", BNC":"");
+-
+- /* If this is a CS8900 then no pnp soft */
+- if (eth_cs_type != CS8900 &&
+- /* Check if the ISA IRQ has been set */
+- (i = readreg(PP_CS8920_ISAINT) & 0xff,
+- (i != 0 && i < CS8920_NO_INTS)))
+- eth_irq = i;
+- else {
+- i = isa_cnf & INT_NO_MASK;
+- if (eth_cs_type == CS8900) {
+- /* the table that follows is dependent
+- upon how you wired up your cs8900
+- in your system. The table is the
+- same as the cs8900 engineering demo
+- board. irq_map also depends on the
+- contents of the table. Also see
+- write_irq, which is the reverse
+- mapping of the table below. */
+- if (i < 4) i = "\012\013\014\005"[i];
+- else printf("\ncs: BUG: isa_config is %d\n", i); }
+- eth_irq = i; }
+-
+- /* Retrieve and print the ethernet address. */
+- for (i=0; i<ETH_ALEN; i++) {
+- nic->node_addr[i] = ((unsigned char *)eeprom_buff)[i];
+- }
+- printf("%!\n", nic->node_addr);
+-
+- /* Set the LineCTL quintuplet based on adapter
+- configuration read from EEPROM */
+- if ((eth_adapter_cnf & A_CNF_EXTND_10B_2) &&
+- (eth_adapter_cnf & A_CNF_LOW_RX_SQUELCH))
+- eth_linectl = LOW_RX_SQUELCH;
+- else
+- eth_linectl = 0;
+-
+- /* check to make sure that they have the "right"
+- hardware available */
+- switch(eth_adapter_cnf & A_CNF_MEDIA_TYPE) {
+- case A_CNF_MEDIA_10B_T: result = eth_adapter_cnf & A_CNF_10B_T;
+- break;
+- case A_CNF_MEDIA_AUI: result = eth_adapter_cnf & A_CNF_AUI;
+- break;
+- case A_CNF_MEDIA_10B_2: result = eth_adapter_cnf & A_CNF_10B_2;
+- break;
+- default: result = eth_adapter_cnf & (A_CNF_10B_T | A_CNF_AUI |
+- A_CNF_10B_2);
+- }
+- if (!result) {
+- printf("cs: EEPROM is configured for unavailable media\n");
+- error:
+- writereg(PP_LineCTL, readreg(PP_LineCTL) &
+- ~(SERIAL_TX_ON | SERIAL_RX_ON));
+- outw(PP_ChipID, eth_nic_base + ADD_PORT);
+- continue;
+- }
+-
+- /* Initialize the card for probing of the attached media */
+- cs89x0_reset(nic);
+-
+- /* set the hardware to the configured choice */
+- switch(eth_adapter_cnf & A_CNF_MEDIA_TYPE) {
+- case A_CNF_MEDIA_10B_T:
+- result = detect_tp();
+- if (!result) {
+- clrline();
+- printf("10Base-T (RJ-45%s",
+- ") has no cable\n"); }
+- /* check "ignore missing media" bit */
+- if (eth_auto_neg_cnf & IMM_BIT)
+- /* Yes! I don't care if I see a link pulse */
+- result = A_CNF_MEDIA_10B_T;
+- break;
+- case A_CNF_MEDIA_AUI:
+- result = detect_aui(nic);
+- if (!result) {
+- clrline();
+- printf("10Base-5 (AUI%s",
+- ") has no cable\n"); }
+- /* check "ignore missing media" bit */
+- if (eth_auto_neg_cnf & IMM_BIT)
+- /* Yes! I don't care if I see a carrrier */
+- result = A_CNF_MEDIA_AUI;
+- break;
+- case A_CNF_MEDIA_10B_2:
+- result = detect_bnc(nic);
+- if (!result) {
+- clrline();
+- printf("10Base-2 (BNC%s",
+- ") has no cable\n"); }
+- /* check "ignore missing media" bit */
+- if (eth_auto_neg_cnf & IMM_BIT)
+- /* Yes! I don't care if I can xmit a packet */
+- result = A_CNF_MEDIA_10B_2;
+- break;
+- case A_CNF_MEDIA_AUTO:
+- writereg(PP_LineCTL, eth_linectl | AUTO_AUI_10BASET);
+- if (eth_adapter_cnf & A_CNF_10B_T)
+- if ((result = detect_tp()) != 0)
+- break;
+- if (eth_adapter_cnf & A_CNF_AUI)
+- if ((result = detect_aui(nic)) != 0)
+- break;
+- if (eth_adapter_cnf & A_CNF_10B_2)
+- if ((result = detect_bnc(nic)) != 0)
+- break;
+- clrline(); printf("no media detected\n");
+- goto error;
+- }
+- clrline();
+- switch(result) {
+- case 0: printf("no network cable attached to configured media\n");
+- goto error;
+- case A_CNF_MEDIA_10B_T: printf("using 10Base-T (RJ-45)\n");
+- break;
+- case A_CNF_MEDIA_AUI: printf("using 10Base-5 (AUI)\n");
+- break;
+- case A_CNF_MEDIA_10B_2: printf("using 10Base-2 (BNC)\n");
+- break;
+- }
+-
+- /* Turn on both receive and transmit operations */
+- writereg(PP_LineCTL, readreg(PP_LineCTL) | SERIAL_RX_ON |
+- SERIAL_TX_ON);
+-
+- break;
+- }
+-
+- if (ioaddr == 0)
+- return (0);
+- nic->reset = cs89x0_reset;
+- nic->poll = cs89x0_poll;
+- nic->transmit = cs89x0_transmit;
+- nic->disable = cs89x0_disable;
+- return (nic);
+-}
+-
+-/*
+- * Local variables:
+- * c-basic-offset: 8
+- * End:
+- */
+-
+diff -Naur grub-0.97.orig/netboot/cs89x0.h grub-0.97/netboot/cs89x0.h
+--- grub-0.97.orig/netboot/cs89x0.h 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/cs89x0.h 1970-01-01 00:00:00.000000000 +0000
+@@ -1,461 +0,0 @@
+-/* Copyright, 1988-1992, Russell Nelson, Crynwr Software
+-
+- This program is free software; you can redistribute it and/or modify
+- it under the terms of the GNU General Public License as published by
+- the Free Software Foundation, version 1.
+-
+- This program is distributed in the hope that it will be useful,
+- but WITHOUT ANY WARRANTY; without even the implied warranty of
+- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- GNU General Public License for more details.
+-
+- You should have received a copy of the GNU General Public License
+- along with this program; if not, write to the Free Software
+- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+-
+-#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
+- /* offset 2h -> Model/Product Number */
+- /* offset 3h -> Chip Revision Number */
+-
+-#define PP_ISAIOB 0x0020 /* IO base address */
+-#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
+-#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
+-#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
+-#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
+-#define PP_ISASOF 0x0026 /* ISA DMA offset */
+-#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
+-#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
+-#define PP_CS8900_ISAMemB 0x002C /* Memory base */
+-#define PP_CS8920_ISAMemB 0x0348 /* */
+-
+-#define PP_ISABootBase 0x0030 /* Boot Prom base */
+-#define PP_ISABootMask 0x0034 /* Boot Prom Mask */
+-
+-/* EEPROM data and command registers */
+-#define PP_EECMD 0x0040 /* NVR Interface Command register */
+-#define PP_EEData 0x0042 /* NVR Interface Data Register */
+-#define PP_DebugReg 0x0044 /* Debug Register */
+-
+-#define PP_RxCFG 0x0102 /* Rx Bus config */
+-#define PP_RxCTL 0x0104 /* Receive Control Register */
+-#define PP_TxCFG 0x0106 /* Transmit Config Register */
+-#define PP_TxCMD 0x0108 /* Transmit Command Register */
+-#define PP_BufCFG 0x010A /* Bus configuration Register */
+-#define PP_LineCTL 0x0112 /* Line Config Register */
+-#define PP_SelfCTL 0x0114 /* Self Command Register */
+-#define PP_BusCTL 0x0116 /* ISA bus control Register */
+-#define PP_TestCTL 0x0118 /* Test Register */
+-#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
+-
+-#define PP_ISQ 0x0120 /* Interrupt Status */
+-#define PP_RxEvent 0x0124 /* Rx Event Register */
+-#define PP_TxEvent 0x0128 /* Tx Event Register */
+-#define PP_BufEvent 0x012C /* Bus Event Register */
+-#define PP_RxMiss 0x0130 /* Receive Miss Count */
+-#define PP_TxCol 0x0132 /* Transmit Collision Count */
+-#define PP_LineST 0x0134 /* Line State Register */
+-#define PP_SelfST 0x0136 /* Self State register */
+-#define PP_BusST 0x0138 /* Bus Status */
+-#define PP_TDR 0x013C /* Time Domain Reflectometry */
+-#define PP_AutoNegST 0x013E /* Auto Neg Status */
+-#define PP_TxCommand 0x0144 /* Tx Command */
+-#define PP_TxLength 0x0146 /* Tx Length */
+-#define PP_LAF 0x0150 /* Hash Table */
+-#define PP_IA 0x0158 /* Physical Address Register */
+-
+-#define PP_RxStatus 0x0400 /* Receive start of frame */
+-#define PP_RxLength 0x0402 /* Receive Length of frame */
+-#define PP_RxFrame 0x0404 /* Receive frame pointer */
+-#define PP_TxFrame 0x0A00 /* Transmit frame pointer */
+-
+-/* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
+-/* can be used as the default I/O base to access the PacketPage Area. */
+-#define DEFAULTIOBASE 0x0300
+-#define FIRST_IO 0x020C /* First I/O port to check */
+-#define LAST_IO 0x037C /* Last I/O port to check (+10h) */
+-#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
+-#define ADD_SIG 0x3000 /* Expected ID signature */
+-
+-#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
+-
+-#ifdef IBMEIPKT
+-#define EISA_ID_SIG 0x4D24 /* IBM */
+-#define PART_NO_SIG 0x1010 /* IBM */
+-#define MONGOOSE_BIT 0x0000 /* IBM */
+-#else
+-#define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
+-#define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
+-#define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
+-#endif
+-
+-#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
+-
+-/* Mask to find out the types of registers */
+-#define REG_TYPE_MASK 0x001F
+-
+-/* Eeprom Commands */
+-#define ERSE_WR_ENBL 0x00F0
+-#define ERSE_WR_DISABLE 0x0000
+-
+-/* Defines Control/Config register quintuplet numbers */
+-#define RX_BUF_CFG 0x0003
+-#define RX_CONTROL 0x0005
+-#define TX_CFG 0x0007
+-#define TX_COMMAND 0x0009
+-#define BUF_CFG 0x000B
+-#define LINE_CONTROL 0x0013
+-#define SELF_CONTROL 0x0015
+-#define BUS_CONTROL 0x0017
+-#define TEST_CONTROL 0x0019
+-
+-/* Defines Status/Count registers quintuplet numbers */
+-#define RX_EVENT 0x0004
+-#define TX_EVENT 0x0008
+-#define BUF_EVENT 0x000C
+-#define RX_MISS_COUNT 0x0010
+-#define TX_COL_COUNT 0x0012
+-#define LINE_STATUS 0x0014
+-#define SELF_STATUS 0x0016
+-#define BUS_STATUS 0x0018
+-#define TDR 0x001C
+-
+-/* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
+-#define SKIP_1 0x0040
+-#define RX_STREAM_ENBL 0x0080
+-#define RX_OK_ENBL 0x0100
+-#define RX_DMA_ONLY 0x0200
+-#define AUTO_RX_DMA 0x0400
+-#define BUFFER_CRC 0x0800
+-#define RX_CRC_ERROR_ENBL 0x1000
+-#define RX_RUNT_ENBL 0x2000
+-#define RX_EXTRA_DATA_ENBL 0x4000
+-
+-/* PP_RxCTL - Receive Control bit definition - Read/write */
+-#define RX_IA_HASH_ACCEPT 0x0040
+-#define RX_PROM_ACCEPT 0x0080
+-#define RX_OK_ACCEPT 0x0100
+-#define RX_MULTCAST_ACCEPT 0x0200
+-#define RX_IA_ACCEPT 0x0400
+-#define RX_BROADCAST_ACCEPT 0x0800
+-#define RX_BAD_CRC_ACCEPT 0x1000
+-#define RX_RUNT_ACCEPT 0x2000
+-#define RX_EXTRA_DATA_ACCEPT 0x4000
+-#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
+-/* Default receive mode - individually addressed, broadcast, and error free */
+-#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
+-
+-/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
+-#define TX_LOST_CRS_ENBL 0x0040
+-#define TX_SQE_ERROR_ENBL 0x0080
+-#define TX_OK_ENBL 0x0100
+-#define TX_LATE_COL_ENBL 0x0200
+-#define TX_JBR_ENBL 0x0400
+-#define TX_ANY_COL_ENBL 0x0800
+-#define TX_16_COL_ENBL 0x8000
+-
+-/* PP_TxCMD - Transmit Command bit definition - Read-only */
+-#define TX_START_4_BYTES 0x0000
+-#define TX_START_64_BYTES 0x0040
+-#define TX_START_128_BYTES 0x0080
+-#define TX_START_ALL_BYTES 0x00C0
+-#define TX_FORCE 0x0100
+-#define TX_ONE_COL 0x0200
+-#define TX_TWO_PART_DEFF_DISABLE 0x0400
+-#define TX_NO_CRC 0x1000
+-#define TX_RUNT 0x2000
+-
+-/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
+-#define GENERATE_SW_INTERRUPT 0x0040
+-#define RX_DMA_ENBL 0x0080
+-#define READY_FOR_TX_ENBL 0x0100
+-#define TX_UNDERRUN_ENBL 0x0200
+-#define RX_MISS_ENBL 0x0400
+-#define RX_128_BYTE_ENBL 0x0800
+-#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
+-#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
+-#define RX_DEST_MATCH_ENBL 0x8000
+-
+-/* PP_LineCTL - Line Control bit definition - Read/write */
+-#define SERIAL_RX_ON 0x0040
+-#define SERIAL_TX_ON 0x0080
+-#define AUI_ONLY 0x0100
+-#define AUTO_AUI_10BASET 0x0200
+-#define MODIFIED_BACKOFF 0x0800
+-#define NO_AUTO_POLARITY 0x1000
+-#define TWO_PART_DEFDIS 0x2000
+-#define LOW_RX_SQUELCH 0x4000
+-
+-/* PP_SelfCTL - Software Self Control bit definition - Read/write */
+-#define POWER_ON_RESET 0x0040
+-#define SW_STOP 0x0100
+-#define SLEEP_ON 0x0200
+-#define AUTO_WAKEUP 0x0400
+-#define HCB0_ENBL 0x1000
+-#define HCB1_ENBL 0x2000
+-#define HCB0 0x4000
+-#define HCB1 0x8000
+-
+-/* PP_BusCTL - ISA Bus Control bit definition - Read/write */
+-#define RESET_RX_DMA 0x0040
+-#define MEMORY_ON 0x0400
+-#define DMA_BURST_MODE 0x0800
+-#define IO_CHANNEL_READY_ON 0x1000
+-#define RX_DMA_SIZE_64K 0x2000
+-#define ENABLE_IRQ 0x8000
+-
+-/* PP_TestCTL - Test Control bit definition - Read/write */
+-#define LINK_OFF 0x0080
+-#define ENDEC_LOOPBACK 0x0200
+-#define AUI_LOOPBACK 0x0400
+-#define BACKOFF_OFF 0x0800
+-#define FAST_TEST 0x8000
+-
+-/* PP_RxEvent - Receive Event Bit definition - Read-only */
+-#define RX_IA_HASHED 0x0040
+-#define RX_DRIBBLE 0x0080
+-#define RX_OK 0x0100
+-#define RX_HASHED 0x0200
+-#define RX_IA 0x0400
+-#define RX_BROADCAST 0x0800
+-#define RX_CRC_ERROR 0x1000
+-#define RX_RUNT 0x2000
+-#define RX_EXTRA_DATA 0x4000
+-
+-#define HASH_INDEX_MASK 0x0FC00
+-
+-/* PP_TxEvent - Transmit Event Bit definition - Read-only */
+-#define TX_LOST_CRS 0x0040
+-#define TX_SQE_ERROR 0x0080
+-#define TX_OK 0x0100
+-#define TX_LATE_COL 0x0200
+-#define TX_JBR 0x0400
+-#define TX_16_COL 0x8000
+-#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
+-#define TX_COL_COUNT_MASK 0x7800
+-
+-/* PP_BufEvent - Buffer Event Bit definition - Read-only */
+-#define SW_INTERRUPT 0x0040
+-#define RX_DMA 0x0080
+-#define READY_FOR_TX 0x0100
+-#define TX_UNDERRUN 0x0200
+-#define RX_MISS 0x0400
+-#define RX_128_BYTE 0x0800
+-#define TX_COL_OVRFLW 0x1000
+-#define RX_MISS_OVRFLW 0x2000
+-#define RX_DEST_MATCH 0x8000
+-
+-/* PP_LineST - Ethernet Line Status bit definition - Read-only */
+-#define LINK_OK 0x0080
+-#define AUI_ON 0x0100
+-#define TENBASET_ON 0x0200
+-#define POLARITY_OK 0x1000
+-#define CRS_OK 0x4000
+-
+-/* PP_SelfST - Chip Software Status bit definition */
+-#define ACTIVE_33V 0x0040
+-#define INIT_DONE 0x0080
+-#define SI_BUSY 0x0100
+-#define EEPROM_PRESENT 0x0200
+-#define EEPROM_OK 0x0400
+-#define EL_PRESENT 0x0800
+-#define EE_SIZE_64 0x1000
+-
+-/* PP_BusST - ISA Bus Status bit definition */
+-#define TX_BID_ERROR 0x0080
+-#define READY_FOR_TX_NOW 0x0100
+-
+-/* PP_AutoNegCTL - Auto Negotiation Control bit definition */
+-#define RE_NEG_NOW 0x0040
+-#define ALLOW_FDX 0x0080
+-#define AUTO_NEG_ENABLE 0x0100
+-#define NLP_ENABLE 0x0200
+-#define FORCE_FDX 0x8000
+-#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
+-#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
+-
+-/* PP_AutoNegST - Auto Negotiation Status bit definition */
+-#define AUTO_NEG_BUSY 0x0080
+-#define FLP_LINK 0x0100
+-#define FLP_LINK_GOOD 0x0800
+-#define LINK_FAULT 0x1000
+-#define HDX_ACTIVE 0x4000
+-#define FDX_ACTIVE 0x8000
+-
+-/* The following block defines the ISQ event types */
+-#define ISQ_RECEIVER_EVENT 0x04
+-#define ISQ_TRANSMITTER_EVENT 0x08
+-#define ISQ_BUFFER_EVENT 0x0c
+-#define ISQ_RX_MISS_EVENT 0x10
+-#define ISQ_TX_COL_EVENT 0x12
+-
+-#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
+-#define ISQ_HIST 16 /* small history buffer */
+-#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
+-
+-#define TXRXBUFSIZE 0x0600
+-#define RXDMABUFSIZE 0x8000
+-#define RXDMASIZE 0x4000
+-#define TXRX_LENGTH_MASK 0x07FF
+-
+-/* rx options bits */
+-#define RCV_WITH_RXON 1 /* Set SerRx ON */
+-#define RCV_COUNTS 2 /* Use Framecnt1 */
+-#define RCV_PONG 4 /* Pong respondent */
+-#define RCV_DONG 8 /* Dong operation */
+-#define RCV_POLLING 0x10 /* Poll RxEvent */
+-#define RCV_ISQ 0x20 /* Use ISQ, int */
+-#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
+-#define RCV_DMA 0x200 /* Set RxDMA only */
+-#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
+-#define RCV_FIXED_DATA 0x800 /* Every frame same */
+-#define RCV_IO 0x1000 /* Use ISA IO only */
+-#define RCV_MEMORY 0x2000 /* Use ISA Memory */
+-
+-#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
+-#define PKT_START PP_TxFrame /* Start of packet RAM */
+-
+-#define RX_FRAME_PORT 0x0000
+-#define TX_FRAME_PORT RX_FRAME_PORT
+-#define TX_CMD_PORT 0x0004
+-#define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
+-#define TX_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */
+-#define TX_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */
+-#define TX_LEN_PORT 0x0006
+-#define ISQ_PORT 0x0008
+-#define ADD_PORT 0x000A
+-#define DATA_PORT 0x000C
+-
+-#define EEPROM_WRITE_EN 0x00F0
+-#define EEPROM_WRITE_DIS 0x0000
+-#define EEPROM_WRITE_CMD 0x0100
+-#define EEPROM_READ_CMD 0x0200
+-
+-/* Receive Header */
+-/* Description of header of each packet in receive area of memory */
+-#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
+-#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
+-#define RBUF_LEN_LOW 2 /* Length of received data - low byte */
+-#define RBUF_LEN_HI 3 /* Length of received data - high byte */
+-#define RBUF_HEAD_LEN 4 /* Length of this header */
+-
+-#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
+-#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
+-
+-/* for bios scan */
+-/* */
+-#ifdef CSDEBUG
+-/* use these values for debugging bios scan */
+-#define BIOS_START_SEG 0x00000
+-#define BIOS_OFFSET_INC 0x0010
+-#else
+-#define BIOS_START_SEG 0x0c000
+-#define BIOS_OFFSET_INC 0x0200
+-#endif
+-
+-#define BIOS_LAST_OFFSET 0x0fc00
+-
+-/* Byte offsets into the EEPROM configuration buffer */
+-#define ISA_CNF_OFFSET 0x6
+-#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
+-#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
+-
+- /* the assumption here is that the bits in the eeprom are generally */
+- /* in the same position as those in the autonegctl register. */
+- /* Of course the IMM bit is not in that register so it must be */
+- /* masked out */
+-#define EE_FORCE_FDX 0x8000
+-#define EE_NLP_ENABLE 0x0200
+-#define EE_AUTO_NEG_ENABLE 0x0100
+-#define EE_ALLOW_FDX 0x0080
+-#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
+-
+-#define IMM_BIT 0x0040 /* ignore missing media */
+-
+-#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
+-#define A_CNF_10B_T 0x0001
+-#define A_CNF_AUI 0x0002
+-#define A_CNF_10B_2 0x0004
+-#define A_CNF_MEDIA_TYPE 0x0060
+-#define A_CNF_MEDIA_AUTO 0x0000
+-#define A_CNF_MEDIA_10B_T 0x0020
+-#define A_CNF_MEDIA_AUI 0x0040
+-#define A_CNF_MEDIA_10B_2 0x0060
+-#define A_CNF_DC_DC_POLARITY 0x0080
+-#define A_CNF_NO_AUTO_POLARITY 0x2000
+-#define A_CNF_LOW_RX_SQUELCH 0x4000
+-#define A_CNF_EXTND_10B_2 0x8000
+-
+-#define PACKET_PAGE_OFFSET 0x8
+-
+-/* Bit definitions for the ISA configuration word from the EEPROM */
+-#define INT_NO_MASK 0x000F
+-#define DMA_NO_MASK 0x0070
+-#define ISA_DMA_SIZE 0x0200
+-#define ISA_AUTO_RxDMA 0x0400
+-#define ISA_RxDMA 0x0800
+-#define DMA_BURST 0x1000
+-#define STREAM_TRANSFER 0x2000
+-#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
+-
+-/* DMA controller registers */
+-#define DMA_BASE 0x00 /* DMA controller base */
+-#define DMA_BASE_2 0x0C0 /* DMA controller base */
+-
+-#define DMA_STAT 0x0D0 /* DMA controller status register */
+-#define DMA_MASK 0x0D4 /* DMA controller mask register */
+-#define DMA_MODE 0x0D6 /* DMA controller mode register */
+-#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
+-
+-/* DMA data */
+-#define DMA_DISABLE 0x04 /* Disable channel n */
+-#define DMA_ENABLE 0x00 /* Enable channel n */
+-/* Demand transfers, incr. address, auto init, writes, ch. n */
+-#define DMA_RX_MODE 0x14
+-/* Demand transfers, incr. address, auto init, reads, ch. n */
+-#define DMA_TX_MODE 0x18
+-
+-#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
+-
+-#define CS8900 0x0000
+-#define CS8920 0x4000
+-#define CS8920M 0x6000
+-#define REVISON_BITS 0x1F00
+-#define EEVER_NUMBER 0x12
+-#define CHKSUM_LEN 0x14
+-#define CHKSUM_VAL 0x0000
+-#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
+-#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
+-#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
+-#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
+-#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
+-
+-#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
+-
+-#define PNP_ADD_PORT 0x0279
+-#define PNP_WRITE_PORT 0x0A79
+-
+-#define GET_PNP_ISA_STRUCT 0x40
+-#define PNP_ISA_STRUCT_LEN 0x06
+-#define PNP_CSN_CNT_OFF 0x01
+-#define PNP_RD_PORT_OFF 0x02
+-#define PNP_FUNCTION_OK 0x00
+-#define PNP_WAKE 0x03
+-#define PNP_RSRC_DATA 0x04
+-#define PNP_RSRC_READY 0x01
+-#define PNP_STATUS 0x05
+-#define PNP_ACTIVATE 0x30
+-#define PNP_CNF_IO_H 0x60
+-#define PNP_CNF_IO_L 0x61
+-#define PNP_CNF_INT 0x70
+-#define PNP_CNF_DMA 0x74
+-#define PNP_CNF_MEM 0x48
+-
+-#define BIT0 1
+-#define BIT15 0x8000
+-
+-/*
+- * Local variables:
+- * c-basic-offset: 8
+- * End:
+- */
+-
+diff -Naur grub-0.97.orig/netboot/cs89x0.txt grub-0.97/netboot/cs89x0.txt
+--- grub-0.97.orig/netboot/cs89x0.txt 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/cs89x0.txt 1970-01-01 00:00:00.000000000 +0000
+@@ -1,26 +0,0 @@
+-Permission is granted to distribute the enclosed cs89x0.[ch] driver
+-only in conjunction with the Etherboot package. The code is
+-ordinarily distributed under the GPL.
+-
+-Russ Nelson, January 2000
+-
+-CREDITS
+-
+-I want to thank
+-
+- Mike Cruse <mcruse@cti-ltd.com>
+- for providing an evaluation NIC and for sponsoring the
+- development of this driver.
+-
+- Randall Sears <sears@crystal.cirrus.com>
+- Deva Bodas <bodas@crystal.cirrus.com>
+- Andreas Kraemer <akraemer@crystal.cirrus.com>
+- Wolfgang Krause <100303.2673@compuserve.com>
+- for excellent technical support and for providing the required
+- programming information. I appreciate Crystal Semiconductor's
+- commitment towards free software.
+-
+- Russell Nelson <nelson@crynwr.com>
+- for writing the Linux device driver for the CS89x0
+- chipset. Russel's code is very well designed and simplified my
+- job a lot.
+diff -Naur grub-0.97.orig/netboot/davicom.c grub-0.97/netboot/davicom.c
+--- grub-0.97.orig/netboot/davicom.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/davicom.c 2005-08-31 19:03:35.000000000 +0000
+@@ -1,12 +1,12 @@
++#ifdef ALLMULTI
++#error multicast support is not yet implemented
++#endif
+ /*
+ DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00
+
+- This driver was ported from Marty Conner's Tulip Etherboot driver.
+- Thanks Marty Connor (mdc@thinguin.org)
+- You can get Tulip driver source file from this URL:
++ This driver was ported from Marty Connor's Tulip Etherboot driver.
++ Thanks Marty Connor (mdc@etherboot.org)
+
+- "http://etherboot.sourceforge..net/#Distribution"
+-
+ This davicom etherboot driver supports DM9009/DM9102/DM9102A/
+ DM9102A+DM9801/DM9102A+DM9802 NICs.
+
+@@ -36,7 +36,6 @@
+ register(CR6)
+ */
+
+-
+ /*********************************************************************/
+ /* Declarations */
+ /*********************************************************************/
+@@ -44,7 +43,6 @@
+ #include "etherboot.h"
+ #include "nic.h"
+ #include "pci.h"
+-#include "cards.h"
+
+ #undef DAVICOM_DEBUG
+ #undef DAVICOM_DEBUG_WHERE
+@@ -99,8 +97,10 @@
+ #define eeprom_delay() inl(ee_addr)
+
+ /* helpful macro if on a big_endian machine for changing byte order.
+- not strictly needed on Intel */
++ not strictly needed on Intel
++ Already defined in Etherboot includes
+ #define le16_to_cpu(val) (val)
++*/
+
+ /* transmit and receive descriptor format */
+ struct txdesc {
+@@ -138,20 +138,12 @@
+ /* transmit descriptor and buffer */
+ #define NTXD 2
+ static struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
+-#ifdef USE_LOWMEM_BUFFER
+-#define txb ((char *)0x10000 - BUFLEN)
+-#else
+ static unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
+-#endif
+
+ /* receive descriptor(s) and buffer(s) */
+ #define NRXD 4
+ static struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
+-#ifdef USE_LOWMEM_BUFFER
+-#define rxb ((char *)0x10000 - NRXD * BUFLEN - BUFLEN)
+-#else
+ static unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
+-#endif
+ static int rxd_tail;
+ static int TxPtr;
+
+@@ -161,15 +153,13 @@
+ /*********************************************************************/
+ static void whereami(const char *str);
+ static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
+-struct nic *davicom_probe(struct nic *nic, unsigned short *io_addrs,
+- struct pci_device *pci);
++static int davicom_probe(struct dev *dev, struct pci_device *pci);
+ static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */
+ static void davicom_reset(struct nic *nic);
+ static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
+ unsigned int s, const char *p);
+-static int davicom_poll(struct nic *nic);
+-static void davicom_disable(struct nic *nic);
+-static void whereami (const char *str);
++static int davicom_poll(struct nic *nic, int retrieve);
++static void davicom_disable(struct dev *dev);
+ #ifdef DAVICOM_DEBUG
+ static void davicom_more(void);
+ #endif /* DAVICOM_DEBUG */
+@@ -184,13 +174,10 @@
+ /*********************************************************************/
+ /* Utility Routines */
+ /*********************************************************************/
+-
+-static inline void whereami (const char *str)
++static inline void whereami(const char *str)
+ {
+-#ifdef DAVICOM_DEBUG_WHERE
+ printf("%s\n", str);
+ /* sleep(2); */
+-#endif
+ }
+
+ #ifdef DAVICOM_DEBUG
+@@ -360,7 +347,7 @@
+ /*
+ Sense media mode and set CR6
+ */
+-static void davicom_media_chk(struct nic * nic)
++static void davicom_media_chk(struct nic * nic __unused)
+ {
+ unsigned long to, csr6;
+
+@@ -446,8 +433,8 @@
+ /* Sten: Set 2 TX descriptor but use one TX buffer because
+ it transmit a packet and wait complete every time. */
+ for (i=0; i<NTXD; i++) {
+- txd[i].buf1addr = &txb[0]; /* Used same TX buffer */
+- txd[i].buf2addr = (unsigned char *)&txd[i+1]; /* Point to Next TX desc */
++ txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */
++ txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */
+ txd[i].buf1sz = 0;
+ txd[i].buf2sz = 0;
+ txd[i].control = 0x184; /* Begin/End/Chain */
+@@ -466,8 +453,8 @@
+
+ /* setup receive descriptor */
+ for (i=0; i<NRXD; i++) {
+- rxd[i].buf1addr = &rxb[i * BUFLEN];
+- rxd[i].buf2addr = (unsigned char *)&rxd[i+1]; /* Point to Next RX desc */
++ rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
++ rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
+ rxd[i].buf1sz = BUFLEN;
+ rxd[i].buf2sz = 0; /* not used */
+ rxd[i].control = 0x4; /* Chain Structure */
+@@ -475,8 +462,8 @@
+ }
+
+ /* Chain the last descriptor to first */
+- txd[NTXD - 1].buf2addr = (unsigned char *)&txd[0];
+- rxd[NRXD - 1].buf2addr = (unsigned char *)&rxd[0];
++ txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
++ rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
+ TxPtr = 0;
+ rxd_tail = 0;
+ }
+@@ -488,7 +475,6 @@
+ static void davicom_reset(struct nic *nic)
+ {
+ unsigned long to;
+- u32 addr_low, addr_high;
+
+ whereami("davicom_reset\n");
+
+@@ -507,8 +493,8 @@
+ davicom_init_chain(nic); /* Sten 10/9 */
+
+ /* Point to receive descriptor */
+- outl((unsigned long)&rxd[0], ioaddr + CSR3);
+- outl((unsigned long)&txd[0], ioaddr + CSR4); /* Sten 10/9 */
++ outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
++ outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */
+
+ /* According phyxcer media mode to set CR6,
+ DM9102/A phyxcer can auto-detect media mode */
+@@ -591,13 +577,15 @@
+ /*********************************************************************/
+ /* eth_poll - Wait for a frame */
+ /*********************************************************************/
+-static int davicom_poll(struct nic *nic)
++static int davicom_poll(struct nic *nic, int retrieve)
+ {
+ whereami("davicom_poll\n");
+
+ if (rxd[rxd_tail].status & 0x80000000)
+ return 0;
+
++ if ( ! retrieve ) return 1;
++
+ whereami("davicom_poll got one\n");
+
+ nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
+@@ -627,10 +615,13 @@
+ /*********************************************************************/
+ /* eth_disable - Disable the interface */
+ /*********************************************************************/
+-static void davicom_disable(struct nic *nic)
++static void davicom_disable(struct dev *dev)
+ {
++ struct nic *nic = (struct nic *)dev;
+ whereami("davicom_disable\n");
+
++ davicom_reset(nic);
++
+ /* disable interrupts */
+ outl(0x00000000, ioaddr + CSR7);
+
+@@ -640,24 +631,43 @@
+ /* Clear the missed-packet counter. */
+ (volatile unsigned long)inl(ioaddr + CSR8);
+ }
++
++
++/*********************************************************************/
++/* eth_irq - enable, disable and force interrupts */
++/*********************************************************************/
++static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
++{
++ switch ( action ) {
++ case DISABLE :
++ break;
++ case ENABLE :
++ break;
++ case FORCE :
++ break;
++ }
++}
++
+
+ /*********************************************************************/
+ /* eth_probe - Look for an adapter */
+ /*********************************************************************/
+-struct nic *davicom_probe(struct nic *nic, unsigned short *io_addrs,
+- struct pci_device *pci)
++static int davicom_probe(struct dev *dev, struct pci_device *pci)
+ {
++ struct nic *nic = (struct nic *)dev;
+ unsigned int i;
+- u32 l1, l2;
+
+ whereami("davicom_probe\n");
+
+- if (io_addrs == 0 || *io_addrs == 0)
++ if (pci->ioaddr == 0)
+ return 0;
+
+ vendor = pci->vendor;
+ dev_id = pci->dev_id;
+- ioaddr = *io_addrs;
++ ioaddr = pci->ioaddr & ~3;
++
++ nic->irqno = 0;
++ nic->ioaddr = pci->ioaddr & ~3;
+
+ /* wakeup chip */
+ pcibios_write_config_dword(pci->bus, pci->devfn, 0x40, 0x00000000);
+@@ -683,10 +693,26 @@
+ /* initialize device */
+ davicom_reset(nic);
+
+- nic->reset = davicom_reset;
++ dev->disable = davicom_disable;
+ nic->poll = davicom_poll;
+ nic->transmit = davicom_transmit;
+- nic->disable = davicom_disable;
++ nic->irq = davicom_irq;
+
+- return nic;
++ return 1;
+ }
++
++static struct pci_id davicom_nics[] = {
++PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100"),
++PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102"),
++PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009"),
++PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132"), /* Needs probably some fixing */
++};
++
++struct pci_driver davicom_driver = {
++ .type = NIC_DRIVER,
++ .name = "DAVICOM",
++ .probe = davicom_probe,
++ .ids = davicom_nics,
++ .id_count = sizeof(davicom_nics)/sizeof(davicom_nics[0]),
++ .class = 0,
++};
+diff -Naur grub-0.97.orig/netboot/depca.c grub-0.97/netboot/depca.c
+--- grub-0.97.orig/netboot/depca.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/depca.c 1970-01-01 00:00:00.000000000 +0000
+@@ -1,752 +0,0 @@
+-/* Etherboot: depca.h merged, comments from Linux driver retained */
+-/* depca.c: A DIGITAL DEPCA & EtherWORKS ethernet driver for linux.
+-
+- Written 1994, 1995 by David C. Davies.
+-
+-
+- Copyright 1994 David C. Davies
+- and
+- United States Government
+- (as represented by the Director, National Security Agency).
+-
+- Copyright 1995 Digital Equipment Corporation.
+-
+-
+- This software may be used and distributed according to the terms of
+- the GNU Public License, incorporated herein by reference.
+-
+- This driver is written for the Digital Equipment Corporation series
+- of DEPCA and EtherWORKS ethernet cards:
+-
+- DEPCA (the original)
+- DE100
+- DE101
+- DE200 Turbo
+- DE201 Turbo
+- DE202 Turbo (TP BNC)
+- DE210
+- DE422 (EISA)
+-
+- The driver has been tested on DE100, DE200 and DE202 cards in a
+- relatively busy network. The DE422 has been tested a little.
+-
+- This driver will NOT work for the DE203, DE204 and DE205 series of
+- cards, since they have a new custom ASIC in place of the AMD LANCE
+- chip. See the 'ewrk3.c' driver in the Linux source tree for running
+- those cards.
+-
+- I have benchmarked the driver with a DE100 at 595kB/s to (542kB/s from)
+- a DECstation 5000/200.
+-
+- The author may be reached at davies@maniac.ultranet.com
+-
+- =========================================================================
+-
+- The driver was originally based on the 'lance.c' driver from Donald
+- Becker which is included with the standard driver distribution for
+- linux. V0.4 is a complete re-write with only the kernel interface
+- remaining from the original code.
+-
+- 1) Lance.c code in /linux/drivers/net/
+- 2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook",
+- AMD, 1992 [(800) 222-9323].
+- 3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)",
+- AMD, Pub. #17881, May 1993.
+- 4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA",
+- AMD, Pub. #16907, May 1992
+- 5) "DEC EtherWORKS LC Ethernet Controller Owners Manual",
+- Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003
+- 6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual",
+- Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003
+- 7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR
+- Digital Equipment Corporation, 1989
+- 8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual",
+- Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001
+-
+-
+- Peter Bauer's depca.c (V0.5) was referred to when debugging V0.1 of this
+- driver.
+-
+- The original DEPCA card requires that the ethernet ROM address counter
+- be enabled to count and has an 8 bit NICSR. The ROM counter enabling is
+- only done when a 0x08 is read as the first address octet (to minimise
+- the chances of writing over some other hardware's I/O register). The
+- NICSR accesses have been changed to byte accesses for all the cards
+- supported by this driver, since there is only one useful bit in the MSB
+- (remote boot timeout) and it is not used. Also, there is a maximum of
+- only 48kB network RAM for this card. My thanks to Torbjorn Lindh for
+- help debugging all this (and holding my feet to the fire until I got it
+- right).
+-
+- The DE200 series boards have on-board 64kB RAM for use as a shared
+- memory network buffer. Only the DE100 cards make use of a 2kB buffer
+- mode which has not been implemented in this driver (only the 32kB and
+- 64kB modes are supported [16kB/48kB for the original DEPCA]).
+-
+- At the most only 2 DEPCA cards can be supported on the ISA bus because
+- there is only provision for two I/O base addresses on each card (0x300
+- and 0x200). The I/O address is detected by searching for a byte sequence
+- in the Ethernet station address PROM at the expected I/O address for the
+- Ethernet PROM. The shared memory base address is 'autoprobed' by
+- looking for the self test PROM and detecting the card name. When a
+- second DEPCA is detected, information is placed in the base_addr
+- variable of the next device structure (which is created if necessary),
+- thus enabling ethif_probe initialization for the device. More than 2
+- EISA cards can be supported, but care will be needed assigning the
+- shared memory to ensure that each slot has the correct IRQ, I/O address
+- and shared memory address assigned.
+-
+- ************************************************************************
+-
+- NOTE: If you are using two ISA DEPCAs, it is important that you assign
+- the base memory addresses correctly. The driver autoprobes I/O 0x300
+- then 0x200. The base memory address for the first device must be less
+- than that of the second so that the auto probe will correctly assign the
+- I/O and memory addresses on the same card. I can't think of a way to do
+- this unambiguously at the moment, since there is nothing on the cards to
+- tie I/O and memory information together.
+-
+- I am unable to test 2 cards together for now, so this code is
+- unchecked. All reports, good or bad, are welcome.
+-
+- ************************************************************************
+-
+- The board IRQ setting must be at an unused IRQ which is auto-probed
+- using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are
+- {2,3,4,5,7}, whereas the DE200 is at {5,9,10,11,15}. Note that IRQ2 is
+- really IRQ9 in machines with 16 IRQ lines.
+-
+- No 16MB memory limitation should exist with this driver as DMA is not
+- used and the common memory area is in low memory on the network card (my
+- current system has 20MB and I've not had problems yet).
+-
+- The ability to load this driver as a loadable module has been added. To
+- utilise this ability, you have to do <8 things:
+-
+- 0) have a copy of the loadable modules code installed on your system.
+- 1) copy depca.c from the /linux/drivers/net directory to your favourite
+- temporary directory.
+- 2) if you wish, edit the source code near line 1530 to reflect the I/O
+- address and IRQ you're using (see also 5).
+- 3) compile depca.c, but include -DMODULE in the command line to ensure
+- that the correct bits are compiled (see end of source code).
+- 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
+- kernel with the depca configuration turned off and reboot.
+- 5) insmod depca.o [irq=7] [io=0x200] [mem=0xd0000] [adapter_name=DE100]
+- [Alan Cox: Changed the code to allow command line irq/io assignments]
+- [Dave Davies: Changed the code to allow command line mem/name
+- assignments]
+- 6) run the net startup bits for your eth?? interface manually
+- (usually /etc/rc.inet[12] at boot time).
+- 7) enjoy!
+-
+- Note that autoprobing is not allowed in loadable modules - the system is
+- already up and running and you're messing with interrupts.
+-
+- To unload a module, turn off the associated interface
+- 'ifconfig eth?? down' then 'rmmod depca'.
+-
+- To assign a base memory address for the shared memory when running as a
+- loadable module, see 5 above. To include the adapter name (if you have
+- no PROM but know the card name) also see 5 above. Note that this last
+- option will not work with kernel built-in depca's.
+-
+- The shared memory assignment for a loadable module makes sense to avoid
+- the 'memory autoprobe' picking the wrong shared memory (for the case of
+- 2 depca's in a PC).
+-
+- ************************************************************************
+- Support for MCA EtherWORKS cards added 11-3-98.
+- Verified to work with up to 2 DE212 cards in a system (although not
+- fully stress-tested).
+-
+- Currently known bugs/limitations:
+-
+- Note: with the MCA stuff as a module, it trusts the MCA configuration,
+- not the command line for IRQ and memory address. You can
+- specify them if you want, but it will throw your values out.
+- You still have to pass the IO address it was configured as
+- though.
+-
+- ************************************************************************
+- TO DO:
+- ------
+-
+-
+- Revision History
+- ----------------
+-
+- Version Date Description
+-
+- 0.1 25-jan-94 Initial writing.
+- 0.2 27-jan-94 Added LANCE TX hardware buffer chaining.
+- 0.3 1-feb-94 Added multiple DEPCA support.
+- 0.31 4-feb-94 Added DE202 recognition.
+- 0.32 19-feb-94 Tidy up. Improve multi-DEPCA support.
+- 0.33 25-feb-94 Fix DEPCA ethernet ROM counter enable.
+- Add jabber packet fix from murf@perftech.com
+- and becker@super.org
+- 0.34 7-mar-94 Fix DEPCA max network memory RAM & NICSR access.
+- 0.35 8-mar-94 Added DE201 recognition. Tidied up.
+- 0.351 30-apr-94 Added EISA support. Added DE422 recognition.
+- 0.36 16-may-94 DE422 fix released.
+- 0.37 22-jul-94 Added MODULE support
+- 0.38 15-aug-94 Added DBR ROM switch in depca_close().
+- Multi DEPCA bug fix.
+- 0.38axp 15-sep-94 Special version for Alpha AXP Linux V1.0.
+- 0.381 12-dec-94 Added DE101 recognition, fix multicast bug.
+- 0.382 9-feb-95 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
+- 0.383 22-feb-95 Fix for conflict with VESA SCSI reported by
+- <stromain@alf.dec.com>
+- 0.384 17-mar-95 Fix a ring full bug reported by <bkm@star.rl.ac.uk>
+- 0.385 3-apr-95 Fix a recognition bug reported by
+- <ryan.niemi@lastfrontier.com>
+- 0.386 21-apr-95 Fix the last fix...sorry, must be galloping senility
+- 0.40 25-May-95 Rewrite for portability & updated.
+- ALPHA support from <jestabro@amt.tay1.dec.com>
+- 0.41 26-Jun-95 Added verify_area() calls in depca_ioctl() from
+- suggestion by <heiko@colossus.escape.de>
+- 0.42 27-Dec-95 Add 'mem' shared memory assignment for loadable
+- modules.
+- Add 'adapter_name' for loadable modules when no PROM.
+- Both above from a suggestion by
+- <pchen@woodruffs121.residence.gatech.edu>.
+- Add new multicasting code.
+- 0.421 22-Apr-96 Fix alloc_device() bug <jari@markkus2.fimr.fi>
+- 0.422 29-Apr-96 Fix depca_hw_init() bug <jari@markkus2.fimr.fi>
+- 0.423 7-Jun-96 Fix module load bug <kmg@barco.be>
+- 0.43 16-Aug-96 Update alloc_device() to conform to de4x5.c
+- 0.44 1-Sep-97 Fix *_probe() to test check_region() first - bug
+- reported by <mmogilvi@elbert.uccs.edu>
+- 0.45 3-Nov-98 Added support for MCA EtherWORKS (DE210/DE212) cards
+- by <tymm@computer.org>
+- 0.451 5-Nov-98 Fixed mca stuff cuz I'm a dummy. <tymm@computer.org>
+- 0.5 14-Nov-98 Re-spin for 2.1.x kernels.
+- 0.51 27-Jun-99 Correct received packet length for CRC from
+- report by <worm@dkik.dk>
+-
+- =========================================================================
+-*/
+-
+-#include "etherboot.h"
+-#include "nic.h"
+-#include "cards.h"
+-
+-/*
+-** I/O addresses. Note that the 2k buffer option is not supported in
+-** this driver.
+-*/
+-#define DEPCA_NICSR ioaddr+0x00 /* Network interface CSR */
+-#define DEPCA_RBI ioaddr+0x02 /* RAM buffer index (2k buffer mode) */
+-#define DEPCA_DATA ioaddr+0x04 /* LANCE registers' data port */
+-#define DEPCA_ADDR ioaddr+0x06 /* LANCE registers' address port */
+-#define DEPCA_HBASE ioaddr+0x08 /* EISA high memory base address reg. */
+-#define DEPCA_PROM ioaddr+0x0c /* Ethernet address ROM data port */
+-#define DEPCA_CNFG ioaddr+0x0c /* EISA Configuration port */
+-#define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */
+-
+-/*
+-** These are LANCE registers addressable through DEPCA_ADDR
+-*/
+-#define CSR0 0
+-#define CSR1 1
+-#define CSR2 2
+-#define CSR3 3
+-
+-/*
+-** NETWORK INTERFACE CSR (NI_CSR) bit definitions
+-*/
+-
+-#define TO 0x0100 /* Time Out for remote boot */
+-#define SHE 0x0080 /* SHadow memory Enable */
+-#define BS 0x0040 /* Bank Select */
+-#define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */
+-#define RBE 0x0010 /* Remote Boot Enable (1->net boot) */
+-#define AAC 0x0008 /* Address ROM Address Counter (1->enable) */
+-#define _128KB 0x0008 /* 128kB Network RAM (1->enable) */
+-#define IM 0x0004 /* Interrupt Mask (1->mask) */
+-#define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */
+-#define LED 0x0001 /* LED control */
+-
+-/*
+-** Control and Status Register 0 (CSR0) bit definitions
+-*/
+-
+-#define ERR 0x8000 /* Error summary */
+-#define BABL 0x4000 /* Babble transmitter timeout error */
+-#define CERR 0x2000 /* Collision Error */
+-#define MISS 0x1000 /* Missed packet */
+-#define MERR 0x0800 /* Memory Error */
+-#define RINT 0x0400 /* Receiver Interrupt */
+-#define TINT 0x0200 /* Transmit Interrupt */
+-#define IDON 0x0100 /* Initialization Done */
+-#define INTR 0x0080 /* Interrupt Flag */
+-#define INEA 0x0040 /* Interrupt Enable */
+-#define RXON 0x0020 /* Receiver on */
+-#define TXON 0x0010 /* Transmitter on */
+-#define TDMD 0x0008 /* Transmit Demand */
+-#define STOP 0x0004 /* Stop */
+-#define STRT 0x0002 /* Start */
+-#define INIT 0x0001 /* Initialize */
+-#define INTM 0xff00 /* Interrupt Mask */
+-#define INTE 0xfff0 /* Interrupt Enable */
+-
+-/*
+-** CONTROL AND STATUS REGISTER 3 (CSR3)
+-*/
+-
+-#define BSWP 0x0004 /* Byte SWaP */
+-#define ACON 0x0002 /* ALE control */
+-#define BCON 0x0001 /* Byte CONtrol */
+-
+-/*
+-** Initialization Block Mode Register
+-*/
+-
+-#define PROM 0x8000 /* Promiscuous Mode */
+-#define EMBA 0x0080 /* Enable Modified Back-off Algorithm */
+-#define INTL 0x0040 /* Internal Loopback */
+-#define DRTY 0x0020 /* Disable Retry */
+-#define COLL 0x0010 /* Force Collision */
+-#define DTCR 0x0008 /* Disable Transmit CRC */
+-#define LOOP 0x0004 /* Loopback */
+-#define DTX 0x0002 /* Disable the Transmitter */
+-#define DRX 0x0001 /* Disable the Receiver */
+-
+-/*
+-** Receive Message Descriptor 1 (RMD1) bit definitions.
+-*/
+-
+-#define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
+-#define R_ERR 0x4000 /* Error Summary */
+-#define R_FRAM 0x2000 /* Framing Error */
+-#define R_OFLO 0x1000 /* Overflow Error */
+-#define R_CRC 0x0800 /* CRC Error */
+-#define R_BUFF 0x0400 /* Buffer Error */
+-#define R_STP 0x0200 /* Start of Packet */
+-#define R_ENP 0x0100 /* End of Packet */
+-
+-/*
+-** Transmit Message Descriptor 1 (TMD1) bit definitions.
+-*/
+-
+-#define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
+-#define T_ERR 0x4000 /* Error Summary */
+-#define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */
+-#define T_MORE 0x1000 /* >1 retry to transmit packet */
+-#define T_ONE 0x0800 /* 1 try needed to transmit the packet */
+-#define T_DEF 0x0400 /* Deferred */
+-#define T_STP 0x02000000 /* Start of Packet */
+-#define T_ENP 0x01000000 /* End of Packet */
+-#define T_FLAGS 0xff000000 /* TX Flags Field */
+-
+-/*
+-** Transmit Message Descriptor 3 (TMD3) bit definitions.
+-*/
+-
+-#define TMD3_BUFF 0x8000 /* BUFFer error */
+-#define TMD3_UFLO 0x4000 /* UnderFLOw error */
+-#define TMD3_RES 0x2000 /* REServed */
+-#define TMD3_LCOL 0x1000 /* Late COLlision */
+-#define TMD3_LCAR 0x0800 /* Loss of CARrier */
+-#define TMD3_RTRY 0x0400 /* ReTRY error */
+-
+-/*
+-** Ethernet PROM defines
+-*/
+-#define PROBE_LENGTH 32
+-
+-/*
+-** Set the number of Tx and Rx buffers. Ensure that the memory requested
+-** here is <= to the amount of shared memory set up by the board switches.
+-** The number of descriptors MUST BE A POWER OF 2.
+-**
+-** total_memory = NUM_RX_DESC*(8+RX_BUFF_SZ) + NUM_TX_DESC*(8+TX_BUFF_SZ)
+-*/
+-#define NUM_RX_DESC 2 /* Number of RX descriptors */
+-#define NUM_TX_DESC 2 /* Number of TX descriptors */
+-#define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */
+-#define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */
+-
+-/*
+-** ISA Bus defines
+-*/
+-#define DEPCA_IO_PORTS {0x300, 0x200, 0}
+-
+-#ifndef DEPCA_MODEL
+-#define DEPCA_MODEL DEPCA
+-#endif
+-
+-static enum {
+- DEPCA, DE100, DE101, DE200, DE201, DE202, DE210, DE212, DE422, unknown
+-} adapter = DEPCA_MODEL;
+-
+-/*
+-** Name <-> Adapter mapping
+-*/
+-
+-static char *adapter_name[] = {
+- "DEPCA",
+- "DE100","DE101",
+- "DE200","DE201","DE202",
+- "DE210","DE212",
+- "DE422",
+- ""
+-};
+-
+-#ifndef DEPCA_RAM_BASE
+-#define DEPCA_RAM_BASE 0xd0000
+-#endif
+-
+-/*
+-** Memory Alignment. Each descriptor is 4 longwords long. To force a
+-** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
+-** DESC_ALIGN. ALIGN aligns the start address of the private memory area
+-** and hence the RX descriptor ring's first entry.
+-*/
+-#define ALIGN4 ((u32)4 - 1) /* 1 longword align */
+-#define ALIGN8 ((u32)8 - 1) /* 2 longword (quadword) align */
+-#define ALIGN ALIGN8 /* Keep the LANCE happy... */
+-
+-typedef long s32;
+-typedef unsigned long u32;
+-typedef short s16;
+-typedef unsigned short u16;
+-typedef char s8;
+-typedef unsigned char u8;
+-
+-/*
+-** The DEPCA Rx and Tx ring descriptors.
+-*/
+-struct depca_rx_desc {
+- volatile s32 base;
+- s16 buf_length; /* This length is negative 2's complement! */
+- s16 msg_length; /* This length is "normal". */
+-};
+-
+-struct depca_tx_desc {
+- volatile s32 base;
+- s16 length; /* This length is negative 2's complement! */
+- s16 misc; /* Errors and TDR info */
+-};
+-
+-#define LA_MASK 0x0000ffff /* LANCE address mask for mapping network RAM
+- to LANCE memory address space */
+-
+-/*
+-** The Lance initialization block, described in databook, in common memory.
+-*/
+-struct depca_init {
+- u16 mode; /* Mode register */
+- u8 phys_addr[ETH_ALEN]; /* Physical ethernet address */
+- u8 mcast_table[8]; /* Multicast Hash Table. */
+- u32 rx_ring; /* Rx ring base pointer & ring length */
+- u32 tx_ring; /* Tx ring base pointer & ring length */
+-};
+-
+-struct depca_private {
+- struct depca_rx_desc *rx_ring;
+- struct depca_tx_desc *tx_ring;
+- struct depca_init init_block; /* Shadow init block */
+- char *rx_memcpy[NUM_RX_DESC];
+- char *tx_memcpy[NUM_TX_DESC];
+- u32 bus_offset; /* ISA bus address offset */
+- u32 sh_mem; /* address of shared mem */
+- u32 dma_buffs; /* Rx & Tx buffer start */
+- int rx_cur, tx_cur; /* Next free ring entry */
+- int txRingMask, rxRingMask;
+- s32 rx_rlen, tx_rlen;
+- /* log2([rt]xRingMask+1) for the descriptors */
+-};
+-
+-static Address mem_start = DEPCA_RAM_BASE;
+-static Address mem_len, offset;
+-static unsigned short ioaddr = 0;
+-static struct depca_private lp;
+-
+-/*
+-** Miscellaneous defines...
+-*/
+-#define STOP_DEPCA \
+- outw(CSR0, DEPCA_ADDR);\
+- outw(STOP, DEPCA_DATA)
+-
+-/* Initialize the lance Rx and Tx descriptor rings. */
+-static void depca_init_ring(struct nic *nic)
+-{
+- int i;
+- u32 p;
+-
+- lp.rx_cur = lp.tx_cur = 0;
+- /* Initialize the base addresses and length of each buffer in the ring */
+- for (i = 0; i <= lp.rxRingMask; i++) {
+- writel((p = lp.dma_buffs + i * RX_BUFF_SZ) | R_OWN, &lp.rx_ring[i].base);
+- writew(-RX_BUFF_SZ, &lp.rx_ring[i].buf_length);
+- lp.rx_memcpy[i] = (char *) (p + lp.bus_offset);
+- }
+- for (i = 0; i <= lp.txRingMask; i++) {
+- writel((p = lp.dma_buffs + (i + lp.txRingMask + 1) * TX_BUFF_SZ) & 0x00ffffff, &lp.tx_ring[i].base);
+- lp.tx_memcpy[i] = (char *) (p + lp.bus_offset);
+- }
+-
+- /* Set up the initialization block */
+- lp.init_block.rx_ring = ((u32) ((u32) lp.rx_ring) & LA_MASK) | lp.rx_rlen;
+- lp.init_block.tx_ring = ((u32) ((u32) lp.tx_ring) & LA_MASK) | lp.tx_rlen;
+- for (i = 0; i < ETH_ALEN; i++)
+- lp.init_block.phys_addr[i] = nic->node_addr[i];
+- lp.init_block.mode = 0x0000; /* Enable the Tx and Rx */
+- memset(lp.init_block.mcast_table, 0, sizeof(lp.init_block.mcast_table));
+-}
+-
+-static void LoadCSRs(void)
+-{
+- outw(CSR1, DEPCA_ADDR); /* initialisation block address LSW */
+- outw((u16) (lp.sh_mem & LA_MASK), DEPCA_DATA);
+- outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */
+- outw((u16) ((lp.sh_mem & LA_MASK) >> 16), DEPCA_DATA);
+- outw(CSR3, DEPCA_ADDR); /* ALE control */
+- outw(ACON, DEPCA_DATA);
+- outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */
+-}
+-
+-static int InitRestartDepca(void)
+-{
+- int i;
+-
+- /* Copy the shadow init_block to shared memory */
+- memcpy_toio((char *)lp.sh_mem, &lp.init_block, sizeof(struct depca_init));
+- outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */
+- outw(INIT, DEPCA_DATA); /* initialise DEPCA */
+-
+- for (i = 0; i < 100 && !(inw(DEPCA_DATA) & IDON); i++)
+- ;
+- if (i < 100) {
+- /* clear IDON by writing a 1, and start LANCE */
+- outw(IDON | STRT, DEPCA_DATA);
+- } else {
+- printf("DEPCA not initialised\n");
+- return (1);
+- }
+- return (0);
+-}
+-
+-/**************************************************************************
+-RESET - Reset adapter
+-***************************************************************************/
+-static void depca_reset(struct nic *nic)
+-{
+- s16 nicsr;
+- int i, j;
+-
+- STOP_DEPCA;
+- nicsr = inb(DEPCA_NICSR);
+- nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | IM);
+- outb(nicsr, DEPCA_NICSR);
+- if (inw(DEPCA_DATA) != STOP)
+- {
+- printf("depca: Cannot stop NIC\n");
+- return;
+- }
+-
+- /* Initialisation block */
+- lp.sh_mem = mem_start;
+- mem_start += sizeof(struct depca_init);
+- /* Tx & Rx descriptors (aligned to a quadword boundary) */
+- mem_start = (mem_start + ALIGN) & ~ALIGN;
+- lp.rx_ring = (struct depca_rx_desc *) mem_start;
+- mem_start += (sizeof(struct depca_rx_desc) * NUM_RX_DESC);
+- lp.tx_ring = (struct depca_tx_desc *) mem_start;
+- mem_start += (sizeof(struct depca_tx_desc) * NUM_TX_DESC);
+-
+- lp.bus_offset = mem_start & 0x00ff0000;
+- /* LANCE re-mapped start address */
+- lp.dma_buffs = mem_start & LA_MASK;
+-
+- /* Finish initialising the ring information. */
+- lp.rxRingMask = NUM_RX_DESC - 1;
+- lp.txRingMask = NUM_TX_DESC - 1;
+-
+- /* Calculate Tx/Rx RLEN size for the descriptors. */
+- for (i = 0, j = lp.rxRingMask; j > 0; i++) {
+- j >>= 1;
+- }
+- lp.rx_rlen = (s32) (i << 29);
+- for (i = 0, j = lp.txRingMask; j > 0; i++) {
+- j >>= 1;
+- }
+- lp.tx_rlen = (s32) (i << 29);
+-
+- /* Load the initialisation block */
+- depca_init_ring(nic);
+- LoadCSRs();
+- InitRestartDepca();
+-}
+-
+-/**************************************************************************
+-POLL - Wait for a frame
+-***************************************************************************/
+-static int depca_poll(struct nic *nic)
+-{
+- int entry;
+- u32 status;
+-
+- entry = lp.rx_cur;
+- if ((status = readl(&lp.rx_ring[entry].base) & R_OWN))
+- return (0);
+- memcpy(nic->packet, lp.rx_memcpy[entry], nic->packetlen = lp.rx_ring[entry].msg_length);
+- lp.rx_ring[entry].base |= R_OWN;
+- lp.rx_cur = (++lp.rx_cur) & lp.rxRingMask;
+- return (1);
+-}
+-
+-/**************************************************************************
+-TRANSMIT - Transmit a frame
+-***************************************************************************/
+-static void depca_transmit(
+- struct nic *nic,
+- const char *d, /* Destination */
+- unsigned int t, /* Type */
+- unsigned int s, /* size */
+- const char *p) /* Packet */
+-{
+- int entry, len;
+- char *mem;
+-
+- /* send the packet to destination */
+- /*
+- ** Caution: the right order is important here... dont
+- ** setup the ownership rights until all the other
+- ** information is in place
+- */
+- mem = lp.tx_memcpy[entry = lp.tx_cur];
+- memcpy_toio(mem, d, ETH_ALEN);
+- memcpy_toio(mem + ETH_ALEN, nic->node_addr, ETH_ALEN);
+- mem[ETH_ALEN * 2] = t >> 8;
+- mem[ETH_ALEN * 2 + 1] = t;
+- memcpy_toio(mem + ETH_HLEN, p, s);
+- s += ETH_HLEN;
+- len = (s < ETH_ZLEN ? ETH_ZLEN : s);
+- /* clean out flags */
+- writel(readl(&lp.tx_ring[entry].base) & ~T_FLAGS, &lp.tx_ring[entry].base);
+- /* clears other error flags */
+- writew(0x0000, &lp.tx_ring[entry].misc);
+- /* packet length in buffer */
+- writew(-len, &lp.tx_ring[entry].length);
+- /* start and end of packet, ownership */
+- writel(readl(&lp.tx_ring[entry].base) | (T_STP|T_ENP|T_OWN), &lp.tx_ring[entry].base);
+- /* update current pointers */
+- lp.tx_cur = (++lp.tx_cur) & lp.txRingMask;
+-}
+-
+-/**************************************************************************
+-DISABLE - Turn off ethernet interface
+-***************************************************************************/
+-static void depca_disable(struct nic *nic)
+-{
+- STOP_DEPCA;
+-}
+-
+-/*
+-** Look for a special sequence in the Ethernet station address PROM that
+-** is common across all DEPCA products. Note that the original DEPCA needs
+-** its ROM address counter to be initialized and enabled. Only enable
+-** if the first address octet is a 0x08 - this minimises the chances of
+-** messing around with some other hardware, but it assumes that this DEPCA
+-** card initialized itself correctly.
+-**
+-** Search the Ethernet address ROM for the signature. Since the ROM address
+-** counter can start at an arbitrary point, the search must include the entire
+-** probe sequence length plus the (length_of_the_signature - 1).
+-** Stop the search IMMEDIATELY after the signature is found so that the
+-** PROM address counter is correctly positioned at the start of the
+-** ethernet address for later read out.
+-*/
+-static int depca_probe1(struct nic *nic)
+-{
+- u8 data, nicsr;
+- /* This is only correct for little endian machines, but then
+- Etherboot doesn't work on anything but a PC */
+- u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA };
+- int i, j;
+- long sum, chksum;
+-
+- data = inb(DEPCA_PROM); /* clear counter on DEPCA */
+- data = inb(DEPCA_PROM); /* read data */
+- if (data == 0x8) {
+- nicsr = inb(DEPCA_NICSR);
+- nicsr |= AAC;
+- outb(nicsr, DEPCA_NICSR);
+- }
+- for (i = 0, j = 0; j < (int)sizeof(sig) && i < PROBE_LENGTH+((int)sizeof(sig))-1; ++i) {
+- data = inb(DEPCA_PROM);
+- if (data == sig[j]) /* track signature */
+- ++j;
+- else
+- j = (data == sig[0]) ? 1 : 0;
+- }
+- if (j != sizeof(sig))
+- return (0);
+- /* put the card in its initial state */
+- STOP_DEPCA;
+- nicsr = ((inb(DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) | IM);
+- outb(nicsr, DEPCA_NICSR);
+- if (inw(DEPCA_DATA) != STOP)
+- return (0);
+- memcpy((char *)mem_start, sig, sizeof(sig));
+- if (memcmp((char *)mem_start, sig, sizeof(sig)) != 0)
+- return (0);
+- for (i = 0, j = 0, sum = 0; j < 3; j++) {
+- sum <<= 1;
+- if (sum > 0xFFFF)
+- sum -= 0xFFFF;
+- sum += (u8)(nic->node_addr[i++] = inb(DEPCA_PROM));
+- sum += (u16)((nic->node_addr[i++] = inb(DEPCA_PROM)) << 8);
+- if (sum > 0xFFFF)
+- sum -= 0xFFFF;
+- }
+- if (sum == 0xFFFF)
+- sum = 0;
+- chksum = (u8)inb(DEPCA_PROM);
+- chksum |= (u16)(inb(DEPCA_PROM) << 8);
+- mem_len = (adapter == DEPCA) ? (48 << 10) : (64 << 10);
+- offset = 0;
+- if (nicsr & BUF) {
+- offset = 0x8000;
+- nicsr &= ~BS;
+- mem_len -= (32 << 10);
+- }
+- if (adapter != DEPCA) /* enable shadow RAM */
+- outb(nicsr |= SHE, DEPCA_NICSR);
+- printf("%s base %#hX, memory [%#hX-%#hX], addr %!",
+- adapter_name[adapter], ioaddr, mem_start, mem_start + mem_len,
+- nic->node_addr);
+- if (sum != chksum)
+- printf(" (bad checksum)");
+- putchar('\n');
+- return (1);
+-}
+-
+-/**************************************************************************
+-PROBE - Look for an adapter, this routine's visible to the outside
+-***************************************************************************/
+-struct nic *depca_probe(struct nic *nic, unsigned short *probe_addrs)
+-{
+- static unsigned short base[] = DEPCA_IO_PORTS;
+- int i;
+-
+- if (probe_addrs == 0 || probe_addrs[0] == 0)
+- probe_addrs = base; /* Use defaults */
+- for (i = 0; (ioaddr = base[i]) != 0; ++i) {
+- if (depca_probe1(nic))
+- break;
+- }
+- if (ioaddr == 0)
+- return (0);
+- depca_reset(nic);
+- /* point to NIC specific routines */
+- nic->reset = depca_reset;
+- nic->poll = depca_poll;
+- nic->transmit = depca_transmit;
+- nic->disable = depca_disable;
+- return (nic);
+-}
+diff -Naur grub-0.97.orig/netboot/dev.h grub-0.97/netboot/dev.h
+--- grub-0.97.orig/netboot/dev.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/dev.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,83 @@
++#ifndef _DEV_H
++#define _DEV_H
++
++#include "isa.h"
++#include "pci.h"
++
++/* Need to check the packing of this struct if Etherboot is ported */
++struct dev_id
++{
++ unsigned short vendor_id;
++ unsigned short device_id;
++ unsigned char bus_type;
++#define PCI_BUS_TYPE 1
++#define ISA_BUS_TYPE 2
++};
++
++/* Dont use sizeof, that will include the padding */
++#define DEV_ID_SIZE 8
++
++
++struct pci_probe_state
++{
++#ifdef CONFIG_PCI
++ struct pci_device dev;
++ int advance;
++#else
++ int dummy;
++#endif
++};
++struct isa_probe_state
++{
++#ifdef CONFIG_ISA
++ const struct isa_driver *driver;
++ int advance;
++#else
++ int dummy;
++#endif
++};
++
++union probe_state
++{
++ struct pci_probe_state pci;
++ struct isa_probe_state isa;
++};
++
++struct dev
++{
++ void (*disable)P((struct dev *));
++ struct dev_id devid; /* device ID string (sent to DHCP server) */
++ int index; /* Index of next device on this controller to probe */
++ int type; /* Type of device I am probing for */
++ int how_probe; /* First, next or awake */
++ int to_probe; /* Flavor of device I am probing */
++ int failsafe; /* Failsafe probe requested */
++ int type_index; /* Index of this device (within type) */
++#define PROBE_NONE 0
++#define PROBE_PCI 1
++#define PROBE_ISA 2
++ union probe_state state;
++};
++
++
++#define NIC_DRIVER 0
++#define DISK_DRIVER 1
++#define FLOPPY_DRIVER 2
++
++#define BRIDGE_DRIVER 1000
++
++#define PROBE_FIRST (-1)
++#define PROBE_NEXT 0
++#define PROBE_AWAKE 1 /* After calling disable bring up the same device */
++
++/* The probe result codes are selected
++ * to allow them to be fed back into the probe
++ * routine and get a successful probe.
++ */
++#define PROBE_FAILED PROBE_FIRST
++#define PROBE_WORKED PROBE_NEXT
++
++extern int probe(struct dev *dev);
++extern void disable(struct dev *dev);
++
++#endif /* _DEV_H */
+diff -Naur grub-0.97.orig/netboot/e1000.c grub-0.97/netboot/e1000.c
+--- grub-0.97.orig/netboot/e1000.c 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/e1000.c 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,3682 @@
++/**************************************************************************
++Etherboot - BOOTP/TFTP Bootstrap Program
++Inter Pro 1000 for Etherboot
++Drivers are port from Intel's Linux driver e1000-4.3.15
++
++***************************************************************************/
++/*******************************************************************************
++
++
++ Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published by the Free
++ Software Foundation; either version 2 of the License, or (at your option)
++ any later version.
++
++ This program is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc., 59
++ Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++
++ The full GNU General Public License is included in this distribution in the
++ file called LICENSE.
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++/*
++ * Copyright (C) Archway Digital Solutions.
++ *
++ * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
++ * 2/9/2002
++ *
++ * Copyright (C) Linux Networx.
++ * Massive upgrade to work with the new intel gigabit NICs.
++ * <ebiederman at lnxi dot com>
++ *
++ * Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
++ * Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
++ *
++ * 01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
++ */
++
++/* to get some global routines like printf */
++#include "etherboot.h"
++/* to get the interface to the body of the program */
++#include "nic.h"
++/* to get the PCI support functions, if this is a PCI NIC */
++#include "pci.h"
++#include "timer.h"
++
++typedef unsigned char *dma_addr_t;
++
++typedef enum {
++ FALSE = 0,
++ TRUE = 1
++} boolean_t;
++
++#define DEBUG 0
++
++
++/* Some pieces of code are disabled with #if 0 ... #endif.
++ * They are not deleted to show where the etherboot driver differs
++ * from the linux driver below the function level.
++ * Some member variables of the hw struct have been eliminated
++ * and the corresponding inplace checks inserted instead.
++ * Pieces such as LED handling that we definitely don't need are deleted.
++ *
++ * The following defines should not be needed normally,
++ * but may be helpful for debugging purposes. */
++
++/* Define this if you want to program the transmission control register
++ * the way the Linux driver does it. */
++#undef LINUX_DRIVER_TCTL
++
++/* Define this to behave more like the Linux driver. */
++#undef LINUX_DRIVER
++
++#include "e1000_hw.h"
++
++/* NIC specific static variables go here */
++static struct e1000_hw hw;
++static char tx_pool[128 + 16];
++static char rx_pool[128 + 16];
++static char packet[2096];
++
++static struct e1000_tx_desc *tx_base;
++static struct e1000_rx_desc *rx_base;
++
++static int tx_tail;
++static int rx_tail, rx_last;
++
++/* Function forward declarations */
++static int e1000_setup_link(struct e1000_hw *hw);
++static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
++static int e1000_setup_copper_link(struct e1000_hw *hw);
++static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
++static void e1000_config_collision_dist(struct e1000_hw *hw);
++static int e1000_config_mac_to_phy(struct e1000_hw *hw);
++static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
++static int e1000_check_for_link(struct e1000_hw *hw);
++static int e1000_wait_autoneg(struct e1000_hw *hw);
++static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
++static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
++static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
++static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
++static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
++static void e1000_phy_hw_reset(struct e1000_hw *hw);
++static int e1000_phy_reset(struct e1000_hw *hw);
++static int e1000_detect_gig_phy(struct e1000_hw *hw);
++
++/* Printing macros... */
++
++#define E1000_ERR(args...) printf("e1000: " args)
++
++#if DEBUG >= 3
++#define E1000_DBG(args...) printf("e1000: " args)
++#else
++#define E1000_DBG(args...)
++#endif
++
++#define MSGOUT(S, A, B) printk(S "\n", A, B)
++#if DEBUG >= 2
++#define DEBUGFUNC(F) DEBUGOUT(F "\n");
++#else
++#define DEBUGFUNC(F)
++#endif
++#if DEBUG >= 1
++#define DEBUGOUT(S) printf(S)
++#define DEBUGOUT1(S,A) printf(S,A)
++#define DEBUGOUT2(S,A,B) printf(S,A,B)
++#define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
++#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
++#else
++#define DEBUGOUT(S)
++#define DEBUGOUT1(S,A)
++#define DEBUGOUT2(S,A,B)
++#define DEBUGOUT3(S,A,B,C)
++#define DEBUGOUT7(S,A,B,C,D,E,F,G)
++#endif
++
++#define E1000_WRITE_REG(a, reg, value) ( \
++ ((a)->mac_type >= e1000_82543) ? \
++ (writel((value), ((a)->hw_addr + E1000_##reg))) : \
++ (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
++
++#define E1000_READ_REG(a, reg) ( \
++ ((a)->mac_type >= e1000_82543) ? \
++ readl((a)->hw_addr + E1000_##reg) : \
++ readl((a)->hw_addr + E1000_82542_##reg))
++
++#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
++ ((a)->mac_type >= e1000_82543) ? \
++ writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
++ writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
++
++#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
++ ((a)->mac_type >= e1000_82543) ? \
++ readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
++ readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
++
++#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
++
++uint32_t
++e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
++{
++ return inl(port);
++}
++
++void
++e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
++{
++ outl(value, port);
++}
++
++static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
++{
++ pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
++}
++
++static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
++{
++ pci_write_config_word(hw->pdev, PCI_COMMAND,
++ hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
++}
++
++/******************************************************************************
++ * Raises the EEPROM's clock input.
++ *
++ * hw - Struct containing variables accessed by shared code
++ * eecd - EECD's current value
++ *****************************************************************************/
++static void
++e1000_raise_ee_clk(struct e1000_hw *hw,
++ uint32_t *eecd)
++{
++ /* Raise the clock input to the EEPROM (by setting the SK bit), and then
++ * wait <delay> microseconds.
++ */
++ *eecd = *eecd | E1000_EECD_SK;
++ E1000_WRITE_REG(hw, EECD, *eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(hw->eeprom.delay_usec);
++}
++
++/******************************************************************************
++ * Lowers the EEPROM's clock input.
++ *
++ * hw - Struct containing variables accessed by shared code
++ * eecd - EECD's current value
++ *****************************************************************************/
++static void
++e1000_lower_ee_clk(struct e1000_hw *hw,
++ uint32_t *eecd)
++{
++ /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
++ * wait 50 microseconds.
++ */
++ *eecd = *eecd & ~E1000_EECD_SK;
++ E1000_WRITE_REG(hw, EECD, *eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(hw->eeprom.delay_usec);
++}
++
++/******************************************************************************
++ * Shift data bits out to the EEPROM.
++ *
++ * hw - Struct containing variables accessed by shared code
++ * data - data to send to the EEPROM
++ * count - number of bits to shift out
++ *****************************************************************************/
++static void
++e1000_shift_out_ee_bits(struct e1000_hw *hw,
++ uint16_t data,
++ uint16_t count)
++{
++ struct e1000_eeprom_info *eeprom = &hw->eeprom;
++ uint32_t eecd;
++ uint32_t mask;
++
++ /* We need to shift "count" bits out to the EEPROM. So, value in the
++ * "data" parameter will be shifted out to the EEPROM one bit at a time.
++ * In order to do this, "data" must be broken down into bits.
++ */
++ mask = 0x01 << (count - 1);
++ eecd = E1000_READ_REG(hw, EECD);
++ if (eeprom->type == e1000_eeprom_microwire) {
++ eecd &= ~E1000_EECD_DO;
++ } else if (eeprom->type == e1000_eeprom_spi) {
++ eecd |= E1000_EECD_DO;
++ }
++ do {
++ /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
++ * and then raising and then lowering the clock (the SK bit controls
++ * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
++ * by setting "DI" to "0" and then raising and then lowering the clock.
++ */
++ eecd &= ~E1000_EECD_DI;
++
++ if(data & mask)
++ eecd |= E1000_EECD_DI;
++
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++
++ udelay(eeprom->delay_usec);
++
++ e1000_raise_ee_clk(hw, &eecd);
++ e1000_lower_ee_clk(hw, &eecd);
++
++ mask = mask >> 1;
++
++ } while(mask);
++
++ /* We leave the "DI" bit set to "0" when we leave this routine. */
++ eecd &= ~E1000_EECD_DI;
++ E1000_WRITE_REG(hw, EECD, eecd);
++}
++
++/******************************************************************************
++ * Shift data bits in from the EEPROM
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static uint16_t
++e1000_shift_in_ee_bits(struct e1000_hw *hw,
++ uint16_t count)
++{
++ uint32_t eecd;
++ uint32_t i;
++ uint16_t data;
++
++ /* In order to read a register from the EEPROM, we need to shift 'count'
++ * bits in from the EEPROM. Bits are "shifted in" by raising the clock
++ * input to the EEPROM (setting the SK bit), and then reading the value of
++ * the "DO" bit. During this "shifting in" process the "DI" bit should
++ * always be clear.
++ */
++
++ eecd = E1000_READ_REG(hw, EECD);
++
++ eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
++ data = 0;
++
++ for(i = 0; i < count; i++) {
++ data = data << 1;
++ e1000_raise_ee_clk(hw, &eecd);
++
++ eecd = E1000_READ_REG(hw, EECD);
++
++ eecd &= ~(E1000_EECD_DI);
++ if(eecd & E1000_EECD_DO)
++ data |= 1;
++
++ e1000_lower_ee_clk(hw, &eecd);
++ }
++
++ return data;
++}
++
++/******************************************************************************
++ * Prepares EEPROM for access
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
++ * function should be called before issuing a command to the EEPROM.
++ *****************************************************************************/
++static int32_t
++e1000_acquire_eeprom(struct e1000_hw *hw)
++{
++ struct e1000_eeprom_info *eeprom = &hw->eeprom;
++ uint32_t eecd, i=0;
++
++ eecd = E1000_READ_REG(hw, EECD);
++
++ /* Request EEPROM Access */
++ if(hw->mac_type > e1000_82544) {
++ eecd |= E1000_EECD_REQ;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ eecd = E1000_READ_REG(hw, EECD);
++ while((!(eecd & E1000_EECD_GNT)) &&
++ (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
++ i++;
++ udelay(5);
++ eecd = E1000_READ_REG(hw, EECD);
++ }
++ if(!(eecd & E1000_EECD_GNT)) {
++ eecd &= ~E1000_EECD_REQ;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ DEBUGOUT("Could not acquire EEPROM grant\n");
++ return -E1000_ERR_EEPROM;
++ }
++ }
++
++ /* Setup EEPROM for Read/Write */
++
++ if (eeprom->type == e1000_eeprom_microwire) {
++ /* Clear SK and DI */
++ eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
++ E1000_WRITE_REG(hw, EECD, eecd);
++
++ /* Set CS */
++ eecd |= E1000_EECD_CS;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ } else if (eeprom->type == e1000_eeprom_spi) {
++ /* Clear SK and CS */
++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
++ E1000_WRITE_REG(hw, EECD, eecd);
++ udelay(1);
++ }
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Returns EEPROM to a "standby" state
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static void
++e1000_standby_eeprom(struct e1000_hw *hw)
++{
++ struct e1000_eeprom_info *eeprom = &hw->eeprom;
++ uint32_t eecd;
++
++ eecd = E1000_READ_REG(hw, EECD);
++
++ if(eeprom->type == e1000_eeprom_microwire) {
++
++ /* Deselect EEPROM */
++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(eeprom->delay_usec);
++
++ /* Clock high */
++ eecd |= E1000_EECD_SK;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(eeprom->delay_usec);
++
++ /* Select EEPROM */
++ eecd |= E1000_EECD_CS;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(eeprom->delay_usec);
++
++ /* Clock low */
++ eecd &= ~E1000_EECD_SK;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(eeprom->delay_usec);
++ } else if(eeprom->type == e1000_eeprom_spi) {
++ /* Toggle CS to flush commands */
++ eecd |= E1000_EECD_CS;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(eeprom->delay_usec);
++ eecd &= ~E1000_EECD_CS;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(eeprom->delay_usec);
++ }
++}
++
++/******************************************************************************
++ * Terminates a command by inverting the EEPROM's chip select pin
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static void
++e1000_release_eeprom(struct e1000_hw *hw)
++{
++ uint32_t eecd;
++
++ eecd = E1000_READ_REG(hw, EECD);
++
++ if (hw->eeprom.type == e1000_eeprom_spi) {
++ eecd |= E1000_EECD_CS; /* Pull CS high */
++ eecd &= ~E1000_EECD_SK; /* Lower SCK */
++
++ E1000_WRITE_REG(hw, EECD, eecd);
++
++ udelay(hw->eeprom.delay_usec);
++ } else if(hw->eeprom.type == e1000_eeprom_microwire) {
++ /* cleanup eeprom */
++
++ /* CS on Microwire is active-high */
++ eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
++
++ E1000_WRITE_REG(hw, EECD, eecd);
++
++ /* Rising edge of clock */
++ eecd |= E1000_EECD_SK;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(hw->eeprom.delay_usec);
++
++ /* Falling edge of clock */
++ eecd &= ~E1000_EECD_SK;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ udelay(hw->eeprom.delay_usec);
++ }
++
++ /* Stop requesting EEPROM access */
++ if(hw->mac_type > e1000_82544) {
++ eecd &= ~E1000_EECD_REQ;
++ E1000_WRITE_REG(hw, EECD, eecd);
++ }
++}
++
++/******************************************************************************
++ * Reads a 16 bit word from the EEPROM.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static int32_t
++e1000_spi_eeprom_ready(struct e1000_hw *hw)
++{
++ uint16_t retry_count = 0;
++ uint8_t spi_stat_reg;
++
++ /* Read "Status Register" repeatedly until the LSB is cleared. The
++ * EEPROM will signal that the command has been completed by clearing
++ * bit 0 of the internal status register. If it's not cleared within
++ * 5 milliseconds, then error out.
++ */
++ retry_count = 0;
++ do {
++ e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
++ hw->eeprom.opcode_bits);
++ spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
++ if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
++ break;
++
++ udelay(5);
++ retry_count += 5;
++
++ } while(retry_count < EEPROM_MAX_RETRY_SPI);
++
++ /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
++ * only 0-5mSec on 5V devices)
++ */
++ if(retry_count >= EEPROM_MAX_RETRY_SPI) {
++ DEBUGOUT("SPI EEPROM Status error\n");
++ return -E1000_ERR_EEPROM;
++ }
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Reads a 16 bit word from the EEPROM.
++ *
++ * hw - Struct containing variables accessed by shared code
++ * offset - offset of word in the EEPROM to read
++ * data - word read from the EEPROM
++ * words - number of words to read
++ *****************************************************************************/
++static int
++e1000_read_eeprom(struct e1000_hw *hw,
++ uint16_t offset,
++ uint16_t words,
++ uint16_t *data)
++{
++ struct e1000_eeprom_info *eeprom = &hw->eeprom;
++ uint32_t i = 0;
++
++ DEBUGFUNC("e1000_read_eeprom");
++
++ /* A check for invalid values: offset too large, too many words, and not
++ * enough words.
++ */
++ if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
++ (words == 0)) {
++ DEBUGOUT("\"words\" parameter out of bounds\n");
++ return -E1000_ERR_EEPROM;
++ }
++
++ /* Prepare the EEPROM for reading */
++ if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
++ return -E1000_ERR_EEPROM;
++
++ if(eeprom->type == e1000_eeprom_spi) {
++ uint16_t word_in;
++ uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
++
++ if(e1000_spi_eeprom_ready(hw)) {
++ e1000_release_eeprom(hw);
++ return -E1000_ERR_EEPROM;
++ }
++
++ e1000_standby_eeprom(hw);
++
++ /* Some SPI eeproms use the 8th address bit embedded in the opcode */
++ if((eeprom->address_bits == 8) && (offset >= 128))
++ read_opcode |= EEPROM_A8_OPCODE_SPI;
++
++ /* Send the READ command (opcode + addr) */
++ e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
++ e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
++
++ /* Read the data. The address of the eeprom internally increments with
++ * each byte (spi) being read, saving on the overhead of eeprom setup
++ * and tear-down. The address counter will roll over if reading beyond
++ * the size of the eeprom, thus allowing the entire memory to be read
++ * starting from any offset. */
++ for (i = 0; i < words; i++) {
++ word_in = e1000_shift_in_ee_bits(hw, 16);
++ data[i] = (word_in >> 8) | (word_in << 8);
++ }
++ } else if(eeprom->type == e1000_eeprom_microwire) {
++ for (i = 0; i < words; i++) {
++ /* Send the READ command (opcode + addr) */
++ e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
++ eeprom->opcode_bits);
++ e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
++ eeprom->address_bits);
++
++ /* Read the data. For microwire, each word requires the overhead
++ * of eeprom setup and tear-down. */
++ data[i] = e1000_shift_in_ee_bits(hw, 16);
++ e1000_standby_eeprom(hw);
++ }
++ }
++
++ /* End this read operation */
++ e1000_release_eeprom(hw);
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Verifies that the EEPROM has a valid checksum
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Reads the first 64 16 bit words of the EEPROM and sums the values read.
++ * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
++ * valid.
++ *****************************************************************************/
++static int
++e1000_validate_eeprom_checksum(struct e1000_hw *hw)
++{
++ uint16_t checksum = 0;
++ uint16_t i, eeprom_data;
++
++ DEBUGFUNC("e1000_validate_eeprom_checksum");
++
++ for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
++ if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
++ DEBUGOUT("EEPROM Read Error\n");
++ return -E1000_ERR_EEPROM;
++ }
++ checksum += eeprom_data;
++ }
++
++ if(checksum == (uint16_t) EEPROM_SUM)
++ return E1000_SUCCESS;
++ else {
++ DEBUGOUT("EEPROM Checksum Invalid\n");
++ return -E1000_ERR_EEPROM;
++ }
++}
++
++/******************************************************************************
++ * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
++ * second function of dual function devices
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static int
++e1000_read_mac_addr(struct e1000_hw *hw)
++{
++ uint16_t offset;
++ uint16_t eeprom_data;
++ int i;
++
++ DEBUGFUNC("e1000_read_mac_addr");
++
++ for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
++ offset = i >> 1;
++ if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
++ DEBUGOUT("EEPROM Read Error\n");
++ return -E1000_ERR_EEPROM;
++ }
++ hw->mac_addr[i] = eeprom_data & 0xff;
++ hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
++ }
++ if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
++ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
++ /* Invert the last bit if this is the second device */
++ hw->mac_addr[5] ^= 1;
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Initializes receive address filters.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Places the MAC address in receive address register 0 and clears the rest
++ * of the receive addresss registers. Clears the multicast table. Assumes
++ * the receiver is in reset when the routine is called.
++ *****************************************************************************/
++static void
++e1000_init_rx_addrs(struct e1000_hw *hw)
++{
++ uint32_t i;
++ uint32_t addr_low;
++ uint32_t addr_high;
++
++ DEBUGFUNC("e1000_init_rx_addrs");
++
++ /* Setup the receive address. */
++ DEBUGOUT("Programming MAC Address into RAR[0]\n");
++ addr_low = (hw->mac_addr[0] |
++ (hw->mac_addr[1] << 8) |
++ (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
++
++ addr_high = (hw->mac_addr[4] |
++ (hw->mac_addr[5] << 8) | E1000_RAH_AV);
++
++ E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
++ E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
++
++ /* Zero out the other 15 receive addresses. */
++ DEBUGOUT("Clearing RAR[1-15]\n");
++ for(i = 1; i < E1000_RAR_ENTRIES; i++) {
++ E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
++ E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
++ }
++}
++
++/******************************************************************************
++ * Clears the VLAN filer table
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static void
++e1000_clear_vfta(struct e1000_hw *hw)
++{
++ uint32_t offset;
++
++ for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
++ E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
++}
++
++/******************************************************************************
++* Writes a value to one of the devices registers using port I/O (as opposed to
++* memory mapped I/O). Only 82544 and newer devices support port I/O. *
++* hw - Struct containing variables accessed by shared code
++* offset - offset to write to * value - value to write
++*****************************************************************************/
++void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){
++ uint32_t io_addr = hw->io_base;
++ uint32_t io_data = hw->io_base + 4;
++ e1000_io_write(hw, io_addr, offset);
++ e1000_io_write(hw, io_data, value);
++}
++
++/******************************************************************************
++ * Set the phy type member in the hw struct.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static int32_t
++e1000_set_phy_type(struct e1000_hw *hw)
++{
++ DEBUGFUNC("e1000_set_phy_type");
++
++ switch(hw->phy_id) {
++ case M88E1000_E_PHY_ID:
++ case M88E1000_I_PHY_ID:
++ case M88E1011_I_PHY_ID:
++ hw->phy_type = e1000_phy_m88;
++ break;
++ case IGP01E1000_I_PHY_ID:
++ hw->phy_type = e1000_phy_igp;
++ break;
++ default:
++ /* Should never have loaded on this device */
++ hw->phy_type = e1000_phy_undefined;
++ return -E1000_ERR_PHY_TYPE;
++ }
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * IGP phy init script - initializes the GbE PHY
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static void
++e1000_phy_init_script(struct e1000_hw *hw)
++{
++ DEBUGFUNC("e1000_phy_init_script");
++
++#if 0
++ /* See e1000_sw_init() of the Linux driver */
++ if(hw->phy_init_script) {
++#else
++ if((hw->mac_type == e1000_82541) ||
++ (hw->mac_type == e1000_82547) ||
++ (hw->mac_type == e1000_82541_rev_2) ||
++ (hw->mac_type == e1000_82547_rev_2)) {
++#endif
++ mdelay(20);
++
++ e1000_write_phy_reg(hw,0x0000,0x0140);
++
++ mdelay(5);
++
++ if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
++ e1000_write_phy_reg(hw, 0x1F95, 0x0001);
++
++ e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
++
++ e1000_write_phy_reg(hw, 0x1F79, 0x0018);
++
++ e1000_write_phy_reg(hw, 0x1F30, 0x1600);
++
++ e1000_write_phy_reg(hw, 0x1F31, 0x0014);
++
++ e1000_write_phy_reg(hw, 0x1F32, 0x161C);
++
++ e1000_write_phy_reg(hw, 0x1F94, 0x0003);
++
++ e1000_write_phy_reg(hw, 0x1F96, 0x003F);
++
++ e1000_write_phy_reg(hw, 0x2010, 0x0008);
++ } else {
++ e1000_write_phy_reg(hw, 0x1F73, 0x0099);
++ }
++
++ e1000_write_phy_reg(hw, 0x0000, 0x3300);
++
++
++ if(hw->mac_type == e1000_82547) {
++ uint16_t fused, fine, coarse;
++
++ /* Move to analog registers page */
++ e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
++
++ if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
++ e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
++
++ fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
++ coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
++
++ if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
++ coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
++ fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
++ } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
++ fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
++
++ fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
++ (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
++ (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
++
++ e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
++ e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
++ IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
++ }
++ }
++ }
++}
++
++/******************************************************************************
++ * Set the mac type member in the hw struct.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static int
++e1000_set_mac_type(struct e1000_hw *hw)
++{
++ DEBUGFUNC("e1000_set_mac_type");
++
++ switch (hw->device_id) {
++ case E1000_DEV_ID_82542:
++ switch (hw->revision_id) {
++ case E1000_82542_2_0_REV_ID:
++ hw->mac_type = e1000_82542_rev2_0;
++ break;
++ case E1000_82542_2_1_REV_ID:
++ hw->mac_type = e1000_82542_rev2_1;
++ break;
++ default:
++ /* Invalid 82542 revision ID */
++ return -E1000_ERR_MAC_TYPE;
++ }
++ break;
++ case E1000_DEV_ID_82543GC_FIBER:
++ case E1000_DEV_ID_82543GC_COPPER:
++ hw->mac_type = e1000_82543;
++ break;
++ case E1000_DEV_ID_82544EI_COPPER:
++ case E1000_DEV_ID_82544EI_FIBER:
++ case E1000_DEV_ID_82544GC_COPPER:
++ case E1000_DEV_ID_82544GC_LOM:
++ hw->mac_type = e1000_82544;
++ break;
++ case E1000_DEV_ID_82540EM:
++ case E1000_DEV_ID_82540EM_LOM:
++ case E1000_DEV_ID_82540EP:
++ case E1000_DEV_ID_82540EP_LOM:
++ case E1000_DEV_ID_82540EP_LP:
++ hw->mac_type = e1000_82540;
++ break;
++ case E1000_DEV_ID_82545EM_COPPER:
++ case E1000_DEV_ID_82545EM_FIBER:
++ hw->mac_type = e1000_82545;
++ break;
++ case E1000_DEV_ID_82545GM_COPPER:
++ case E1000_DEV_ID_82545GM_FIBER:
++ case E1000_DEV_ID_82545GM_SERDES:
++ hw->mac_type = e1000_82545_rev_3;
++ break;
++ case E1000_DEV_ID_82546EB_COPPER:
++ case E1000_DEV_ID_82546EB_FIBER:
++ case E1000_DEV_ID_82546EB_QUAD_COPPER:
++ hw->mac_type = e1000_82546;
++ break;
++ case E1000_DEV_ID_82546GB_COPPER:
++ case E1000_DEV_ID_82546GB_FIBER:
++ case E1000_DEV_ID_82546GB_SERDES:
++ hw->mac_type = e1000_82546_rev_3;
++ break;
++ case E1000_DEV_ID_82541EI:
++ case E1000_DEV_ID_82541EI_MOBILE:
++ hw->mac_type = e1000_82541;
++ break;
++ case E1000_DEV_ID_82541ER:
++ case E1000_DEV_ID_82541GI:
++ case E1000_DEV_ID_82541GI_MOBILE:
++ hw->mac_type = e1000_82541_rev_2;
++ break;
++ case E1000_DEV_ID_82547EI:
++ hw->mac_type = e1000_82547;
++ break;
++ case E1000_DEV_ID_82547GI:
++ hw->mac_type = e1000_82547_rev_2;
++ break;
++ default:
++ /* Should never have loaded on this device */
++ return -E1000_ERR_MAC_TYPE;
++ }
++
++ return E1000_SUCCESS;
++}
++
++/*****************************************************************************
++ * Set media type and TBI compatibility.
++ *
++ * hw - Struct containing variables accessed by shared code
++ * **************************************************************************/
++static void
++e1000_set_media_type(struct e1000_hw *hw)
++{
++ uint32_t status;
++
++ DEBUGFUNC("e1000_set_media_type");
++
++ if(hw->mac_type != e1000_82543) {
++ /* tbi_compatibility is only valid on 82543 */
++ hw->tbi_compatibility_en = FALSE;
++ }
++
++ switch (hw->device_id) {
++ case E1000_DEV_ID_82545GM_SERDES:
++ case E1000_DEV_ID_82546GB_SERDES:
++ hw->media_type = e1000_media_type_internal_serdes;
++ break;
++ default:
++ if(hw->mac_type >= e1000_82543) {
++ status = E1000_READ_REG(hw, STATUS);
++ if(status & E1000_STATUS_TBIMODE) {
++ hw->media_type = e1000_media_type_fiber;
++ /* tbi_compatibility not valid on fiber */
++ hw->tbi_compatibility_en = FALSE;
++ } else {
++ hw->media_type = e1000_media_type_copper;
++ }
++ } else {
++ /* This is an 82542 (fiber only) */
++ hw->media_type = e1000_media_type_fiber;
++ }
++ }
++}
++
++/******************************************************************************
++ * Reset the transmit and receive units; mask and clear all interrupts.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static void
++e1000_reset_hw(struct e1000_hw *hw)
++{
++ uint32_t ctrl;
++ uint32_t ctrl_ext;
++ uint32_t icr;
++ uint32_t manc;
++
++ DEBUGFUNC("e1000_reset_hw");
++
++ /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
++ if(hw->mac_type == e1000_82542_rev2_0) {
++ DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
++ e1000_pci_clear_mwi(hw);
++ }
++
++ /* Clear interrupt mask to stop board from generating interrupts */
++ DEBUGOUT("Masking off all interrupts\n");
++ E1000_WRITE_REG(hw, IMC, 0xffffffff);
++
++ /* Disable the Transmit and Receive units. Then delay to allow
++ * any pending transactions to complete before we hit the MAC with
++ * the global reset.
++ */
++ E1000_WRITE_REG(hw, RCTL, 0);
++ E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
++ E1000_WRITE_FLUSH(hw);
++
++ /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
++ hw->tbi_compatibility_on = FALSE;
++
++ /* Delay to allow any outstanding PCI transactions to complete before
++ * resetting the device
++ */
++ mdelay(10);
++
++ ctrl = E1000_READ_REG(hw, CTRL);
++
++ /* Must reset the PHY before resetting the MAC */
++ if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
++ E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
++ mdelay(5);
++ }
++
++ /* Issue a global reset to the MAC. This will reset the chip's
++ * transmit, receive, DMA, and link units. It will not effect
++ * the current PCI configuration. The global reset bit is self-
++ * clearing, and should clear within a microsecond.
++ */
++ DEBUGOUT("Issuing a global reset to MAC\n");
++
++ switch(hw->mac_type) {
++ case e1000_82544:
++ case e1000_82540:
++ case e1000_82545:
++ case e1000_82546:
++ case e1000_82541:
++ case e1000_82541_rev_2:
++ /* These controllers can't ack the 64-bit write when issuing the
++ * reset, so use IO-mapping as a workaround to issue the reset */
++ E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
++ break;
++ case e1000_82545_rev_3:
++ case e1000_82546_rev_3:
++ /* Reset is performed on a shadow of the control register */
++ E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
++ break;
++ default:
++ E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
++ break;
++ }
++
++ /* After MAC reset, force reload of EEPROM to restore power-on settings to
++ * device. Later controllers reload the EEPROM automatically, so just wait
++ * for reload to complete.
++ */
++ switch(hw->mac_type) {
++ case e1000_82542_rev2_0:
++ case e1000_82542_rev2_1:
++ case e1000_82543:
++ case e1000_82544:
++ /* Wait for reset to complete */
++ udelay(10);
++ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
++ ctrl_ext |= E1000_CTRL_EXT_EE_RST;
++ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
++ E1000_WRITE_FLUSH(hw);
++ /* Wait for EEPROM reload */
++ mdelay(2);
++ break;
++ case e1000_82541:
++ case e1000_82541_rev_2:
++ case e1000_82547:
++ case e1000_82547_rev_2:
++ /* Wait for EEPROM reload */
++ mdelay(20);
++ break;
++ default:
++ /* Wait for EEPROM reload (it happens automatically) */
++ mdelay(5);
++ break;
++ }
++
++ /* Disable HW ARPs on ASF enabled adapters */
++ if(hw->mac_type >= e1000_82540) {
++ manc = E1000_READ_REG(hw, MANC);
++ manc &= ~(E1000_MANC_ARP_EN);
++ E1000_WRITE_REG(hw, MANC, manc);
++ }
++
++ if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
++ e1000_phy_init_script(hw);
++ }
++
++ /* Clear interrupt mask to stop board from generating interrupts */
++ DEBUGOUT("Masking off all interrupts\n");
++ E1000_WRITE_REG(hw, IMC, 0xffffffff);
++
++ /* Clear any pending interrupt events. */
++ icr = E1000_READ_REG(hw, ICR);
++
++ /* If MWI was previously enabled, reenable it. */
++ if(hw->mac_type == e1000_82542_rev2_0) {
++#ifdef LINUX_DRIVER
++ if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
++#endif
++ e1000_pci_set_mwi(hw);
++ }
++}
++
++/******************************************************************************
++ * Performs basic configuration of the adapter.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Assumes that the controller has previously been reset and is in a
++ * post-reset uninitialized state. Initializes the receive address registers,
++ * multicast table, and VLAN filter table. Calls routines to setup link
++ * configuration and flow control settings. Clears all on-chip counters. Leaves
++ * the transmit and receive units disabled and uninitialized.
++ *****************************************************************************/
++static int
++e1000_init_hw(struct e1000_hw *hw)
++{
++ uint32_t ctrl, status;
++ uint32_t i;
++ int32_t ret_val;
++ uint16_t pcix_cmd_word;
++ uint16_t pcix_stat_hi_word;
++ uint16_t cmd_mmrbc;
++ uint16_t stat_mmrbc;
++ e1000_bus_type bus_type = e1000_bus_type_unknown;
++
++ DEBUGFUNC("e1000_init_hw");
++
++ /* Set the media type and TBI compatibility */
++ e1000_set_media_type(hw);
++
++ /* Disabling VLAN filtering. */
++ DEBUGOUT("Initializing the IEEE VLAN\n");
++ E1000_WRITE_REG(hw, VET, 0);
++
++ e1000_clear_vfta(hw);
++
++ /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
++ if(hw->mac_type == e1000_82542_rev2_0) {
++ DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
++ e1000_pci_clear_mwi(hw);
++ E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
++ E1000_WRITE_FLUSH(hw);
++ mdelay(5);
++ }
++
++ /* Setup the receive address. This involves initializing all of the Receive
++ * Address Registers (RARs 0 - 15).
++ */
++ e1000_init_rx_addrs(hw);
++
++ /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
++ if(hw->mac_type == e1000_82542_rev2_0) {
++ E1000_WRITE_REG(hw, RCTL, 0);
++ E1000_WRITE_FLUSH(hw);
++ mdelay(1);
++#ifdef LINUX_DRIVER
++ if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
++#endif
++ e1000_pci_set_mwi(hw);
++ }
++
++ /* Zero out the Multicast HASH table */
++ DEBUGOUT("Zeroing the MTA\n");
++ for(i = 0; i < E1000_MC_TBL_SIZE; i++)
++ E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
++
++#if 0
++ /* Set the PCI priority bit correctly in the CTRL register. This
++ * determines if the adapter gives priority to receives, or if it
++ * gives equal priority to transmits and receives.
++ */
++ if(hw->dma_fairness) {
++ ctrl = E1000_READ_REG(hw, CTRL);
++ E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
++ }
++#endif
++
++ switch(hw->mac_type) {
++ case e1000_82545_rev_3:
++ case e1000_82546_rev_3:
++ break;
++ default:
++ if (hw->mac_type >= e1000_82543) {
++ /* See e1000_get_bus_info() of the Linux driver */
++ status = E1000_READ_REG(hw, STATUS);
++ bus_type = (status & E1000_STATUS_PCIX_MODE) ?
++ e1000_bus_type_pcix : e1000_bus_type_pci;
++ }
++
++ /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
++ if(bus_type == e1000_bus_type_pcix) {
++ pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
++ pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
++ cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
++ PCIX_COMMAND_MMRBC_SHIFT;
++ stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
++ PCIX_STATUS_HI_MMRBC_SHIFT;
++ if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
++ stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
++ if(cmd_mmrbc > stat_mmrbc) {
++ pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
++ pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
++ pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
++ }
++ }
++ break;
++ }
++
++ /* Call a subroutine to configure the link and setup flow control. */
++ ret_val = e1000_setup_link(hw);
++
++ /* Set the transmit descriptor write-back policy */
++ if(hw->mac_type > e1000_82544) {
++ ctrl = E1000_READ_REG(hw, TXDCTL);
++ ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
++ E1000_WRITE_REG(hw, TXDCTL, ctrl);
++ }
++
++#if 0
++ /* Clear all of the statistics registers (clear on read). It is
++ * important that we do this after we have tried to establish link
++ * because the symbol error count will increment wildly if there
++ * is no link.
++ */
++ e1000_clear_hw_cntrs(hw);
++#endif
++
++ return ret_val;
++}
++
++/******************************************************************************
++ * Adjust SERDES output amplitude based on EEPROM setting.
++ *
++ * hw - Struct containing variables accessed by shared code.
++ *****************************************************************************/
++static int32_t
++e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
++{
++ uint16_t eeprom_data;
++ int32_t ret_val;
++
++ DEBUGFUNC("e1000_adjust_serdes_amplitude");
++
++ if(hw->media_type != e1000_media_type_internal_serdes)
++ return E1000_SUCCESS;
++
++ switch(hw->mac_type) {
++ case e1000_82545_rev_3:
++ case e1000_82546_rev_3:
++ break;
++ default:
++ return E1000_SUCCESS;
++ }
++
++ if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
++ &eeprom_data))) {
++ return ret_val;
++ }
++
++ if(eeprom_data != EEPROM_RESERVED_WORD) {
++ /* Adjust SERDES output amplitude only. */
++ eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
++ if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
++ eeprom_data)))
++ return ret_val;
++ }
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Configures flow control and link settings.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Determines which flow control settings to use. Calls the apropriate media-
++ * specific link configuration function. Configures the flow control settings.
++ * Assuming the adapter has a valid link partner, a valid link should be
++ * established. Assumes the hardware has previously been reset and the
++ * transmitter and receiver are not enabled.
++ *****************************************************************************/
++static int
++e1000_setup_link(struct e1000_hw *hw)
++{
++ uint32_t ctrl_ext;
++ int32_t ret_val;
++ uint16_t eeprom_data;
++
++ DEBUGFUNC("e1000_setup_link");
++
++ /* Read and store word 0x0F of the EEPROM. This word contains bits
++ * that determine the hardware's default PAUSE (flow control) mode,
++ * a bit that determines whether the HW defaults to enabling or
++ * disabling auto-negotiation, and the direction of the
++ * SW defined pins. If there is no SW over-ride of the flow
++ * control setting, then the variable hw->fc will
++ * be initialized based on a value in the EEPROM.
++ */
++ if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
++ DEBUGOUT("EEPROM Read Error\n");
++ return -E1000_ERR_EEPROM;
++ }
++
++ if(hw->fc == e1000_fc_default) {
++ if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
++ hw->fc = e1000_fc_none;
++ else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
++ EEPROM_WORD0F_ASM_DIR)
++ hw->fc = e1000_fc_tx_pause;
++ else
++ hw->fc = e1000_fc_full;
++ }
++
++ /* We want to save off the original Flow Control configuration just
++ * in case we get disconnected and then reconnected into a different
++ * hub or switch with different Flow Control capabilities.
++ */
++ if(hw->mac_type == e1000_82542_rev2_0)
++ hw->fc &= (~e1000_fc_tx_pause);
++
++#if 0
++ /* See e1000_sw_init() of the Linux driver */
++ if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
++#else
++ if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
++#endif
++ hw->fc &= (~e1000_fc_rx_pause);
++
++#if 0
++ hw->original_fc = hw->fc;
++#endif
++
++ DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
++
++ /* Take the 4 bits from EEPROM word 0x0F that determine the initial
++ * polarity value for the SW controlled pins, and setup the
++ * Extended Device Control reg with that info.
++ * This is needed because one of the SW controlled pins is used for
++ * signal detection. So this should be done before e1000_setup_pcs_link()
++ * or e1000_phy_setup() is called.
++ */
++ if(hw->mac_type == e1000_82543) {
++ ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
++ SWDPIO__EXT_SHIFT);
++ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
++ }
++
++ /* Call the necessary subroutine to configure the link. */
++ ret_val = (hw->media_type == e1000_media_type_copper) ?
++ e1000_setup_copper_link(hw) :
++ e1000_setup_fiber_serdes_link(hw);
++ if (ret_val < 0) {
++ return ret_val;
++ }
++
++ /* Initialize the flow control address, type, and PAUSE timer
++ * registers to their default values. This is done even if flow
++ * control is disabled, because it does not hurt anything to
++ * initialize these registers.
++ */
++ DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
++
++ E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
++ E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
++ E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
++#if 0
++ E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
++#else
++ E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
++#endif
++
++ /* Set the flow control receive threshold registers. Normally,
++ * these registers will be set to a default threshold that may be
++ * adjusted later by the driver's runtime code. However, if the
++ * ability to transmit pause frames in not enabled, then these
++ * registers will be set to 0.
++ */
++ if(!(hw->fc & e1000_fc_tx_pause)) {
++ E1000_WRITE_REG(hw, FCRTL, 0);
++ E1000_WRITE_REG(hw, FCRTH, 0);
++ } else {
++ /* We need to set up the Receive Threshold high and low water marks
++ * as well as (optionally) enabling the transmission of XON frames.
++ */
++#if 0
++ if(hw->fc_send_xon) {
++ E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
++ E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
++ } else {
++ E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
++ E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
++ }
++#else
++ E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
++ E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
++#endif
++ }
++ return ret_val;
++}
++
++/******************************************************************************
++ * Sets up link for a fiber based or serdes based adapter
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Manipulates Physical Coding Sublayer functions in order to configure
++ * link. Assumes the hardware has been previously reset and the transmitter
++ * and receiver are not enabled.
++ *****************************************************************************/
++static int
++e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
++{
++ uint32_t ctrl;
++ uint32_t status;
++ uint32_t txcw = 0;
++ uint32_t i;
++ uint32_t signal = 0;
++ int32_t ret_val;
++
++ DEBUGFUNC("e1000_setup_fiber_serdes_link");
++
++ /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
++ * set when the optics detect a signal. On older adapters, it will be
++ * cleared when there is a signal. This applies to fiber media only.
++ * If we're on serdes media, adjust the output amplitude to value set in
++ * the EEPROM.
++ */
++ ctrl = E1000_READ_REG(hw, CTRL);
++ if(hw->media_type == e1000_media_type_fiber)
++ signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
++
++ if((ret_val = e1000_adjust_serdes_amplitude(hw)))
++ return ret_val;
++
++ /* Take the link out of reset */
++ ctrl &= ~(E1000_CTRL_LRST);
++
++#if 0
++ /* Adjust VCO speed to improve BER performance */
++ if((ret_val = e1000_set_vco_speed(hw)))
++ return ret_val;
++#endif
++
++ e1000_config_collision_dist(hw);
++
++ /* Check for a software override of the flow control settings, and setup
++ * the device accordingly. If auto-negotiation is enabled, then software
++ * will have to set the "PAUSE" bits to the correct value in the Tranmsit
++ * Config Word Register (TXCW) and re-start auto-negotiation. However, if
++ * auto-negotiation is disabled, then software will have to manually
++ * configure the two flow control enable bits in the CTRL register.
++ *
++ * The possible values of the "fc" parameter are:
++ * 0: Flow control is completely disabled
++ * 1: Rx flow control is enabled (we can receive pause frames, but
++ * not send pause frames).
++ * 2: Tx flow control is enabled (we can send pause frames but we do
++ * not support receiving pause frames).
++ * 3: Both Rx and TX flow control (symmetric) are enabled.
++ */
++ switch (hw->fc) {
++ case e1000_fc_none:
++ /* Flow control is completely disabled by a software over-ride. */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
++ break;
++ case e1000_fc_rx_pause:
++ /* RX Flow control is enabled and TX Flow control is disabled by a
++ * software over-ride. Since there really isn't a way to advertise
++ * that we are capable of RX Pause ONLY, we will advertise that we
++ * support both symmetric and asymmetric RX PAUSE. Later, we will
++ * disable the adapter's ability to send PAUSE frames.
++ */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
++ break;
++ case e1000_fc_tx_pause:
++ /* TX Flow control is enabled, and RX Flow control is disabled, by a
++ * software over-ride.
++ */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
++ break;
++ case e1000_fc_full:
++ /* Flow control (both RX and TX) is enabled by a software over-ride. */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
++ break;
++ default:
++ DEBUGOUT("Flow control param set incorrectly\n");
++ return -E1000_ERR_CONFIG;
++ break;
++ }
++
++ /* Since auto-negotiation is enabled, take the link out of reset (the link
++ * will be in reset, because we previously reset the chip). This will
++ * restart auto-negotiation. If auto-neogtiation is successful then the
++ * link-up status bit will be set and the flow control enable bits (RFCE
++ * and TFCE) will be set according to their negotiated value.
++ */
++ DEBUGOUT("Auto-negotiation enabled\n");
++
++ E1000_WRITE_REG(hw, TXCW, txcw);
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ E1000_WRITE_FLUSH(hw);
++
++ hw->txcw = txcw;
++ mdelay(1);
++
++ /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
++ * indication in the Device Status Register. Time-out if a link isn't
++ * seen in 500 milliseconds seconds (Auto-negotiation should complete in
++ * less than 500 milliseconds even if the other end is doing it in SW).
++ * For internal serdes, we just assume a signal is present, then poll.
++ */
++ if(hw->media_type == e1000_media_type_internal_serdes ||
++ (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
++ DEBUGOUT("Looking for Link\n");
++ for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
++ mdelay(10);
++ status = E1000_READ_REG(hw, STATUS);
++ if(status & E1000_STATUS_LU) break;
++ }
++ if(i == (LINK_UP_TIMEOUT / 10)) {
++ DEBUGOUT("Never got a valid link from auto-neg!!!\n");
++ hw->autoneg_failed = 1;
++ /* AutoNeg failed to achieve a link, so we'll call
++ * e1000_check_for_link. This routine will force the link up if
++ * we detect a signal. This will allow us to communicate with
++ * non-autonegotiating link partners.
++ */
++ if((ret_val = e1000_check_for_link(hw))) {
++ DEBUGOUT("Error while checking for link\n");
++ return ret_val;
++ }
++ hw->autoneg_failed = 0;
++ } else {
++ hw->autoneg_failed = 0;
++ DEBUGOUT("Valid Link Found\n");
++ }
++ } else {
++ DEBUGOUT("No Signal Detected\n");
++ }
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++* Detects which PHY is present and the speed and duplex
++*
++* hw - Struct containing variables accessed by shared code
++******************************************************************************/
++static int
++e1000_setup_copper_link(struct e1000_hw *hw)
++{
++ uint32_t ctrl;
++ int32_t ret_val;
++ uint16_t i;
++ uint16_t phy_data;
++
++ DEBUGFUNC("e1000_setup_copper_link");
++
++ ctrl = E1000_READ_REG(hw, CTRL);
++ /* With 82543, we need to force speed and duplex on the MAC equal to what
++ * the PHY speed and duplex configuration is. In addition, we need to
++ * perform a hardware reset on the PHY to take it out of reset.
++ */
++ if(hw->mac_type > e1000_82543) {
++ ctrl |= E1000_CTRL_SLU;
++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ } else {
++ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ e1000_phy_hw_reset(hw);
++ }
++
++ /* Make sure we have a valid PHY */
++ if((ret_val = e1000_detect_gig_phy(hw))) {
++ DEBUGOUT("Error, did not detect valid phy.\n");
++ return ret_val;
++ }
++ DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
++
++ if(hw->mac_type <= e1000_82543 ||
++ hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
++#if 0
++ hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
++ hw->phy_reset_disable = FALSE;
++
++ if(!hw->phy_reset_disable) {
++#else
++ hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
++#endif
++ if (hw->phy_type == e1000_phy_igp) {
++
++ if((ret_val = e1000_phy_reset(hw))) {
++ DEBUGOUT("Error Resetting the PHY\n");
++ return ret_val;
++ }
++
++ /* Wait 10ms for MAC to configure PHY from eeprom settings */
++ mdelay(15);
++
++#if 0
++ /* disable lplu d3 during driver init */
++ if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
++ DEBUGOUT("Error Disabling LPLU D3\n");
++ return ret_val;
++ }
++
++ /* Configure mdi-mdix settings */
++ if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
++ &phy_data)))
++ return ret_val;
++
++ if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
++ hw->dsp_config_state = e1000_dsp_config_disabled;
++ /* Force MDI for IGP B-0 PHY */
++ phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
++ IGP01E1000_PSCR_FORCE_MDI_MDIX);
++ hw->mdix = 1;
++
++ } else {
++ hw->dsp_config_state = e1000_dsp_config_enabled;
++ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
++
++ switch (hw->mdix) {
++ case 1:
++ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
++ break;
++ case 2:
++ phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
++ break;
++ case 0:
++ default:
++ phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
++ break;
++ }
++ }
++ if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
++ phy_data)))
++ return ret_val;
++
++ /* set auto-master slave resolution settings */
++ e1000_ms_type phy_ms_setting = hw->master_slave;
++
++ if(hw->ffe_config_state == e1000_ffe_config_active)
++ hw->ffe_config_state = e1000_ffe_config_enabled;
++
++ if(hw->dsp_config_state == e1000_dsp_config_activated)
++ hw->dsp_config_state = e1000_dsp_config_enabled;
++#endif
++
++ /* when autonegotiation advertisment is only 1000Mbps then we
++ * should disable SmartSpeed and enable Auto MasterSlave
++ * resolution as hardware default. */
++ if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
++ /* Disable SmartSpeed */
++ if((ret_val = e1000_read_phy_reg(hw,
++ IGP01E1000_PHY_PORT_CONFIG,
++ &phy_data)))
++ return ret_val;
++ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
++ if((ret_val = e1000_write_phy_reg(hw,
++ IGP01E1000_PHY_PORT_CONFIG,
++ phy_data)))
++ return ret_val;
++ /* Set auto Master/Slave resolution process */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
++ &phy_data)))
++ return ret_val;
++ phy_data &= ~CR_1000T_MS_ENABLE;
++ if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
++ phy_data)))
++ return ret_val;
++ }
++
++ if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
++ &phy_data)))
++ return ret_val;
++
++#if 0
++ /* load defaults for future use */
++ hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
++ ((phy_data & CR_1000T_MS_VALUE) ?
++ e1000_ms_force_master :
++ e1000_ms_force_slave) :
++ e1000_ms_auto;
++
++ switch (phy_ms_setting) {
++ case e1000_ms_force_master:
++ phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
++ break;
++ case e1000_ms_force_slave:
++ phy_data |= CR_1000T_MS_ENABLE;
++ phy_data &= ~(CR_1000T_MS_VALUE);
++ break;
++ case e1000_ms_auto:
++ phy_data &= ~CR_1000T_MS_ENABLE;
++ default:
++ break;
++ }
++#endif
++
++ if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
++ phy_data)))
++ return ret_val;
++ } else {
++ /* Enable CRS on TX. This must be set for half-duplex operation. */
++ if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
++ &phy_data)))
++ return ret_val;
++
++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
++
++ /* Options:
++ * MDI/MDI-X = 0 (default)
++ * 0 - Auto for all speeds
++ * 1 - MDI mode
++ * 2 - MDI-X mode
++ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
++ */
++#if 0
++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
++
++ switch (hw->mdix) {
++ case 1:
++ phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
++ break;
++ case 2:
++ phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
++ break;
++ case 3:
++ phy_data |= M88E1000_PSCR_AUTO_X_1000T;
++ break;
++ case 0:
++ default:
++#endif
++ phy_data |= M88E1000_PSCR_AUTO_X_MODE;
++#if 0
++ break;
++ }
++#endif
++
++ /* Options:
++ * disable_polarity_correction = 0 (default)
++ * Automatic Correction for Reversed Cable Polarity
++ * 0 - Disabled
++ * 1 - Enabled
++ */
++ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
++ if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
++ phy_data)))
++ return ret_val;
++
++ /* Force TX_CLK in the Extended PHY Specific Control Register
++ * to 25MHz clock.
++ */
++ if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
++ &phy_data)))
++ return ret_val;
++
++ phy_data |= M88E1000_EPSCR_TX_CLK_25;
++
++#ifdef LINUX_DRIVER
++ if (hw->phy_revision < M88E1011_I_REV_4) {
++#endif
++ /* Configure Master and Slave downshift values */
++ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
++ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
++ if((ret_val = e1000_write_phy_reg(hw,
++ M88E1000_EXT_PHY_SPEC_CTRL,
++ phy_data)))
++ return ret_val;
++ }
++
++ /* SW Reset the PHY so all changes take effect */
++ if((ret_val = e1000_phy_reset(hw))) {
++ DEBUGOUT("Error Resetting the PHY\n");
++ return ret_val;
++#ifdef LINUX_DRIVER
++ }
++#endif
++ }
++
++ /* Options:
++ * autoneg = 1 (default)
++ * PHY will advertise value(s) parsed from
++ * autoneg_advertised and fc
++ * autoneg = 0
++ * PHY will be set to 10H, 10F, 100H, or 100F
++ * depending on value parsed from forced_speed_duplex.
++ */
++
++ /* Is autoneg enabled? This is enabled by default or by software
++ * override. If so, call e1000_phy_setup_autoneg routine to parse the
++ * autoneg_advertised and fc options. If autoneg is NOT enabled, then
++ * the user should have provided a speed/duplex override. If so, then
++ * call e1000_phy_force_speed_duplex to parse and set this up.
++ */
++ /* Perform some bounds checking on the hw->autoneg_advertised
++ * parameter. If this variable is zero, then set it to the default.
++ */
++ hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
++
++ /* If autoneg_advertised is zero, we assume it was not defaulted
++ * by the calling code so we set to advertise full capability.
++ */
++ if(hw->autoneg_advertised == 0)
++ hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
++
++ DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
++ if((ret_val = e1000_phy_setup_autoneg(hw))) {
++ DEBUGOUT("Error Setting up Auto-Negotiation\n");
++ return ret_val;
++ }
++ DEBUGOUT("Restarting Auto-Neg\n");
++
++ /* Restart auto-negotiation by setting the Auto Neg Enable bit and
++ * the Auto Neg Restart bit in the PHY control register.
++ */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
++ return ret_val;
++
++ phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
++ if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
++ return ret_val;
++
++#if 0
++ /* Does the user want to wait for Auto-Neg to complete here, or
++ * check at a later time (for example, callback routine).
++ */
++ if(hw->wait_autoneg_complete) {
++ if((ret_val = e1000_wait_autoneg(hw))) {
++ DEBUGOUT("Error while waiting for autoneg to complete\n");
++ return ret_val;
++ }
++ }
++#else
++ /* If we do not wait for autonegotiation to complete I
++ * do not see a valid link status.
++ */
++ if((ret_val = e1000_wait_autoneg(hw))) {
++ DEBUGOUT("Error while waiting for autoneg to complete\n");
++ return ret_val;
++ }
++#endif
++ } /* !hw->phy_reset_disable */
++
++ /* Check link status. Wait up to 100 microseconds for link to become
++ * valid.
++ */
++ for(i = 0; i < 10; i++) {
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
++ return ret_val;
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
++ return ret_val;
++
++ if(phy_data & MII_SR_LINK_STATUS) {
++ /* We have link, so we need to finish the config process:
++ * 1) Set up the MAC to the current PHY speed/duplex
++ * if we are on 82543. If we
++ * are on newer silicon, we only need to configure
++ * collision distance in the Transmit Control Register.
++ * 2) Set up flow control on the MAC to that established with
++ * the link partner.
++ */
++ if(hw->mac_type >= e1000_82544) {
++ e1000_config_collision_dist(hw);
++ } else {
++ if((ret_val = e1000_config_mac_to_phy(hw))) {
++ DEBUGOUT("Error configuring MAC to PHY settings\n");
++ return ret_val;
++ }
++ }
++ if((ret_val = e1000_config_fc_after_link_up(hw))) {
++ DEBUGOUT("Error Configuring Flow Control\n");
++ return ret_val;
++ }
++#if 0
++ if(hw->phy_type == e1000_phy_igp) {
++ if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
++ DEBUGOUT("Error Configuring DSP after link up\n");
++ return ret_val;
++ }
++ }
++#endif
++ DEBUGOUT("Valid link established!!!\n");
++ return E1000_SUCCESS;
++ }
++ udelay(10);
++ }
++
++ DEBUGOUT("Unable to establish link!!!\n");
++ return -E1000_ERR_NOLINK;
++}
++
++/******************************************************************************
++* Configures PHY autoneg and flow control advertisement settings
++*
++* hw - Struct containing variables accessed by shared code
++******************************************************************************/
++static int
++e1000_phy_setup_autoneg(struct e1000_hw *hw)
++{
++ int32_t ret_val;
++ uint16_t mii_autoneg_adv_reg;
++ uint16_t mii_1000t_ctrl_reg;
++
++ DEBUGFUNC("e1000_phy_setup_autoneg");
++
++ /* Read the MII Auto-Neg Advertisement Register (Address 4). */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
++ &mii_autoneg_adv_reg)))
++ return ret_val;
++
++ /* Read the MII 1000Base-T Control Register (Address 9). */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
++ return ret_val;
++
++ /* Need to parse both autoneg_advertised and fc and set up
++ * the appropriate PHY registers. First we will parse for
++ * autoneg_advertised software override. Since we can advertise
++ * a plethora of combinations, we need to check each bit
++ * individually.
++ */
++
++ /* First we clear all the 10/100 mb speed bits in the Auto-Neg
++ * Advertisement Register (Address 4) and the 1000 mb speed bits in
++ * the 1000Base-T Control Register (Address 9).
++ */
++ mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
++ mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
++
++ DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
++
++ /* Do we want to advertise 10 Mb Half Duplex? */
++ if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
++ DEBUGOUT("Advertise 10mb Half duplex\n");
++ mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
++ }
++
++ /* Do we want to advertise 10 Mb Full Duplex? */
++ if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
++ DEBUGOUT("Advertise 10mb Full duplex\n");
++ mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
++ }
++
++ /* Do we want to advertise 100 Mb Half Duplex? */
++ if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
++ DEBUGOUT("Advertise 100mb Half duplex\n");
++ mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
++ }
++
++ /* Do we want to advertise 100 Mb Full Duplex? */
++ if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
++ DEBUGOUT("Advertise 100mb Full duplex\n");
++ mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
++ }
++
++ /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
++ if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
++ DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
++ }
++
++ /* Do we want to advertise 1000 Mb Full Duplex? */
++ if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
++ DEBUGOUT("Advertise 1000mb Full duplex\n");
++ mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
++ }
++
++ /* Check for a software override of the flow control settings, and
++ * setup the PHY advertisement registers accordingly. If
++ * auto-negotiation is enabled, then software will have to set the
++ * "PAUSE" bits to the correct value in the Auto-Negotiation
++ * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
++ *
++ * The possible values of the "fc" parameter are:
++ * 0: Flow control is completely disabled
++ * 1: Rx flow control is enabled (we can receive pause frames
++ * but not send pause frames).
++ * 2: Tx flow control is enabled (we can send pause frames
++ * but we do not support receiving pause frames).
++ * 3: Both Rx and TX flow control (symmetric) are enabled.
++ * other: No software override. The flow control configuration
++ * in the EEPROM is used.
++ */
++ switch (hw->fc) {
++ case e1000_fc_none: /* 0 */
++ /* Flow control (RX & TX) is completely disabled by a
++ * software over-ride.
++ */
++ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
++ break;
++ case e1000_fc_rx_pause: /* 1 */
++ /* RX Flow control is enabled, and TX Flow control is
++ * disabled, by a software over-ride.
++ */
++ /* Since there really isn't a way to advertise that we are
++ * capable of RX Pause ONLY, we will advertise that we
++ * support both symmetric and asymmetric RX PAUSE. Later
++ * (in e1000_config_fc_after_link_up) we will disable the
++ *hw's ability to send PAUSE frames.
++ */
++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
++ break;
++ case e1000_fc_tx_pause: /* 2 */
++ /* TX Flow control is enabled, and RX Flow control is
++ * disabled, by a software over-ride.
++ */
++ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
++ mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
++ break;
++ case e1000_fc_full: /* 3 */
++ /* Flow control (both RX and TX) is enabled by a software
++ * over-ride.
++ */
++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
++ break;
++ default:
++ DEBUGOUT("Flow control param set incorrectly\n");
++ return -E1000_ERR_CONFIG;
++ }
++
++ if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
++ mii_autoneg_adv_reg)))
++ return ret_val;
++
++ DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
++
++ if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
++ return ret_val;
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++* Sets the collision distance in the Transmit Control register
++*
++* hw - Struct containing variables accessed by shared code
++*
++* Link should have been established previously. Reads the speed and duplex
++* information from the Device Status register.
++******************************************************************************/
++static void
++e1000_config_collision_dist(struct e1000_hw *hw)
++{
++ uint32_t tctl;
++
++ tctl = E1000_READ_REG(hw, TCTL);
++
++ tctl &= ~E1000_TCTL_COLD;
++ tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
++
++ E1000_WRITE_REG(hw, TCTL, tctl);
++ E1000_WRITE_FLUSH(hw);
++}
++
++/******************************************************************************
++* Sets MAC speed and duplex settings to reflect the those in the PHY
++*
++* hw - Struct containing variables accessed by shared code
++* mii_reg - data to write to the MII control register
++*
++* The contents of the PHY register containing the needed information need to
++* be passed in.
++******************************************************************************/
++static int
++e1000_config_mac_to_phy(struct e1000_hw *hw)
++{
++ uint32_t ctrl;
++ int32_t ret_val;
++ uint16_t phy_data;
++
++ DEBUGFUNC("e1000_config_mac_to_phy");
++
++ /* Read the Device Control Register and set the bits to Force Speed
++ * and Duplex.
++ */
++ ctrl = E1000_READ_REG(hw, CTRL);
++ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
++ ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
++
++ /* Set up duplex in the Device Control and Transmit Control
++ * registers depending on negotiated values.
++ */
++ if (hw->phy_type == e1000_phy_igp) {
++ if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
++ &phy_data)))
++ return ret_val;
++
++ if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
++ else ctrl &= ~E1000_CTRL_FD;
++
++ e1000_config_collision_dist(hw);
++
++ /* Set up speed in the Device Control register depending on
++ * negotiated values.
++ */
++ if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
++ IGP01E1000_PSSR_SPEED_1000MBPS)
++ ctrl |= E1000_CTRL_SPD_1000;
++ else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
++ IGP01E1000_PSSR_SPEED_100MBPS)
++ ctrl |= E1000_CTRL_SPD_100;
++ } else {
++ if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
++ &phy_data)))
++ return ret_val;
++
++ if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
++ else ctrl &= ~E1000_CTRL_FD;
++
++ e1000_config_collision_dist(hw);
++
++ /* Set up speed in the Device Control register depending on
++ * negotiated values.
++ */
++ if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
++ ctrl |= E1000_CTRL_SPD_1000;
++ else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
++ ctrl |= E1000_CTRL_SPD_100;
++ }
++ /* Write the configured values back to the Device Control Reg. */
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Forces the MAC's flow control settings.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Sets the TFCE and RFCE bits in the device control register to reflect
++ * the adapter settings. TFCE and RFCE need to be explicitly set by
++ * software when a Copper PHY is used because autonegotiation is managed
++ * by the PHY rather than the MAC. Software must also configure these
++ * bits when link is forced on a fiber connection.
++ *****************************************************************************/
++static int
++e1000_force_mac_fc(struct e1000_hw *hw)
++{
++ uint32_t ctrl;
++
++ DEBUGFUNC("e1000_force_mac_fc");
++
++ /* Get the current configuration of the Device Control Register */
++ ctrl = E1000_READ_REG(hw, CTRL);
++
++ /* Because we didn't get link via the internal auto-negotiation
++ * mechanism (we either forced link or we got link via PHY
++ * auto-neg), we have to manually enable/disable transmit an
++ * receive flow control.
++ *
++ * The "Case" statement below enables/disable flow control
++ * according to the "hw->fc" parameter.
++ *
++ * The possible values of the "fc" parameter are:
++ * 0: Flow control is completely disabled
++ * 1: Rx flow control is enabled (we can receive pause
++ * frames but not send pause frames).
++ * 2: Tx flow control is enabled (we can send pause frames
++ * frames but we do not receive pause frames).
++ * 3: Both Rx and TX flow control (symmetric) is enabled.
++ * other: No other values should be possible at this point.
++ */
++
++ switch (hw->fc) {
++ case e1000_fc_none:
++ ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
++ break;
++ case e1000_fc_rx_pause:
++ ctrl &= (~E1000_CTRL_TFCE);
++ ctrl |= E1000_CTRL_RFCE;
++ break;
++ case e1000_fc_tx_pause:
++ ctrl &= (~E1000_CTRL_RFCE);
++ ctrl |= E1000_CTRL_TFCE;
++ break;
++ case e1000_fc_full:
++ ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
++ break;
++ default:
++ DEBUGOUT("Flow control param set incorrectly\n");
++ return -E1000_ERR_CONFIG;
++ }
++
++ /* Disable TX Flow Control for 82542 (rev 2.0) */
++ if(hw->mac_type == e1000_82542_rev2_0)
++ ctrl &= (~E1000_CTRL_TFCE);
++
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Configures flow control settings after link is established
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Should be called immediately after a valid link has been established.
++ * Forces MAC flow control settings if link was forced. When in MII/GMII mode
++ * and autonegotiation is enabled, the MAC flow control settings will be set
++ * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
++ * and RFCE bits will be automaticaly set to the negotiated flow control mode.
++ *****************************************************************************/
++static int
++e1000_config_fc_after_link_up(struct e1000_hw *hw)
++{
++ int32_t ret_val;
++ uint16_t mii_status_reg;
++ uint16_t mii_nway_adv_reg;
++ uint16_t mii_nway_lp_ability_reg;
++ uint16_t speed;
++ uint16_t duplex;
++
++ DEBUGFUNC("e1000_config_fc_after_link_up");
++
++ /* Check for the case where we have fiber media and auto-neg failed
++ * so we had to force link. In this case, we need to force the
++ * configuration of the MAC to match the "fc" parameter.
++ */
++ if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
++ ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) {
++ if((ret_val = e1000_force_mac_fc(hw))) {
++ DEBUGOUT("Error forcing flow control settings\n");
++ return ret_val;
++ }
++ }
++
++ /* Check for the case where we have copper media and auto-neg is
++ * enabled. In this case, we need to check and see if Auto-Neg
++ * has completed, and if so, how the PHY and link partner has
++ * flow control configured.
++ */
++ if(hw->media_type == e1000_media_type_copper) {
++ /* Read the MII Status Register and check to see if AutoNeg
++ * has completed. We read this twice because this reg has
++ * some "sticky" (latched) bits.
++ */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
++ return ret_val;
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
++ return ret_val;
++
++ if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
++ /* The AutoNeg process has completed, so we now need to
++ * read both the Auto Negotiation Advertisement Register
++ * (Address 4) and the Auto_Negotiation Base Page Ability
++ * Register (Address 5) to determine how flow control was
++ * negotiated.
++ */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
++ &mii_nway_adv_reg)))
++ return ret_val;
++ if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
++ &mii_nway_lp_ability_reg)))
++ return ret_val;
++
++ /* Two bits in the Auto Negotiation Advertisement Register
++ * (Address 4) and two bits in the Auto Negotiation Base
++ * Page Ability Register (Address 5) determine flow control
++ * for both the PHY and the link partner. The following
++ * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
++ * 1999, describes these PAUSE resolution bits and how flow
++ * control is determined based upon these settings.
++ * NOTE: DC = Don't Care
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
++ *-------|---------|-------|---------|--------------------
++ * 0 | 0 | DC | DC | e1000_fc_none
++ * 0 | 1 | 0 | DC | e1000_fc_none
++ * 0 | 1 | 1 | 0 | e1000_fc_none
++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
++ * 1 | 0 | 0 | DC | e1000_fc_none
++ * 1 | DC | 1 | DC | e1000_fc_full
++ * 1 | 1 | 0 | 0 | e1000_fc_none
++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
++ *
++ */
++ /* Are both PAUSE bits set to 1? If so, this implies
++ * Symmetric Flow Control is enabled at both ends. The
++ * ASM_DIR bits are irrelevant per the spec.
++ *
++ * For Symmetric Flow Control:
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
++ *-------|---------|-------|---------|--------------------
++ * 1 | DC | 1 | DC | e1000_fc_full
++ *
++ */
++ if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
++ /* Now we need to check if the user selected RX ONLY
++ * of pause frames. In this case, we had to advertise
++ * FULL flow control because we could not advertise RX
++ * ONLY. Hence, we must now check to see if we need to
++ * turn OFF the TRANSMISSION of PAUSE frames.
++ */
++#if 0
++ if(hw->original_fc == e1000_fc_full) {
++ hw->fc = e1000_fc_full;
++#else
++ if(hw->fc == e1000_fc_full) {
++#endif
++ DEBUGOUT("Flow Control = FULL.\r\n");
++ } else {
++ hw->fc = e1000_fc_rx_pause;
++ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
++ }
++ }
++ /* For receiving PAUSE frames ONLY.
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
++ *-------|---------|-------|---------|--------------------
++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
++ *
++ */
++ else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
++ hw->fc = e1000_fc_tx_pause;
++ DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
++ }
++ /* For transmitting PAUSE frames ONLY.
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
++ *-------|---------|-------|---------|--------------------
++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
++ *
++ */
++ else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
++ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
++ hw->fc = e1000_fc_rx_pause;
++ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
++ }
++ /* Per the IEEE spec, at this point flow control should be
++ * disabled. However, we want to consider that we could
++ * be connected to a legacy switch that doesn't advertise
++ * desired flow control, but can be forced on the link
++ * partner. So if we advertised no flow control, that is
++ * what we will resolve to. If we advertised some kind of
++ * receive capability (Rx Pause Only or Full Flow Control)
++ * and the link partner advertised none, we will configure
++ * ourselves to enable Rx Flow Control only. We can do
++ * this safely for two reasons: If the link partner really
++ * didn't want flow control enabled, and we enable Rx, no
++ * harm done since we won't be receiving any PAUSE frames
++ * anyway. If the intent on the link partner was to have
++ * flow control enabled, then by us enabling RX only, we
++ * can at least receive pause frames and process them.
++ * This is a good idea because in most cases, since we are
++ * predominantly a server NIC, more times than not we will
++ * be asked to delay transmission of packets than asking
++ * our link partner to pause transmission of frames.
++ */
++#if 0
++ else if(hw->original_fc == e1000_fc_none ||
++ hw->original_fc == e1000_fc_tx_pause) {
++#else
++ else if(hw->fc == e1000_fc_none)
++ DEBUGOUT("Flow Control = NONE.\r\n");
++ else if(hw->fc == e1000_fc_tx_pause) {
++#endif
++ hw->fc = e1000_fc_none;
++ DEBUGOUT("Flow Control = NONE.\r\n");
++ } else {
++ hw->fc = e1000_fc_rx_pause;
++ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
++ }
++
++ /* Now we need to do one last check... If we auto-
++ * negotiated to HALF DUPLEX, flow control should not be
++ * enabled per IEEE 802.3 spec.
++ */
++ e1000_get_speed_and_duplex(hw, &speed, &duplex);
++
++ if(duplex == HALF_DUPLEX)
++ hw->fc = e1000_fc_none;
++
++ /* Now we call a subroutine to actually force the MAC
++ * controller to use the correct flow control settings.
++ */
++ if((ret_val = e1000_force_mac_fc(hw))) {
++ DEBUGOUT("Error forcing flow control settings\n");
++ return ret_val;
++ }
++ } else {
++ DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
++ }
++ }
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Checks to see if the link status of the hardware has changed.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *
++ * Called by any function that needs to check the link status of the adapter.
++ *****************************************************************************/
++static int
++e1000_check_for_link(struct e1000_hw *hw)
++{
++ uint32_t rxcw;
++ uint32_t ctrl;
++ uint32_t status;
++ uint32_t rctl;
++ uint32_t signal = 0;
++ int32_t ret_val;
++ uint16_t phy_data;
++ uint16_t lp_capability;
++
++ DEBUGFUNC("e1000_check_for_link");
++
++ /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
++ * set when the optics detect a signal. On older adapters, it will be
++ * cleared when there is a signal. This applies to fiber media only.
++ */
++ if(hw->media_type == e1000_media_type_fiber)
++ signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
++
++ ctrl = E1000_READ_REG(hw, CTRL);
++ status = E1000_READ_REG(hw, STATUS);
++ rxcw = E1000_READ_REG(hw, RXCW);
++
++ /* If we have a copper PHY then we only want to go out to the PHY
++ * registers to see if Auto-Neg has completed and/or if our link
++ * status has changed. The get_link_status flag will be set if we
++ * receive a Link Status Change interrupt or we have Rx Sequence
++ * Errors.
++ */
++#if 0
++ if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
++#else
++ if(hw->media_type == e1000_media_type_copper) {
++#endif
++ /* First we want to see if the MII Status Register reports
++ * link. If so, then we want to get the current speed/duplex
++ * of the PHY.
++ * Read the register twice since the link bit is sticky.
++ */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
++ return ret_val;
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
++ return ret_val;
++
++ if(phy_data & MII_SR_LINK_STATUS) {
++#if 0
++ hw->get_link_status = FALSE;
++#endif
++ } else {
++ /* No link detected */
++ return -E1000_ERR_NOLINK;
++ }
++
++ /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
++ * have Si on board that is 82544 or newer, Auto
++ * Speed Detection takes care of MAC speed/duplex
++ * configuration. So we only need to configure Collision
++ * Distance in the MAC. Otherwise, we need to force
++ * speed/duplex on the MAC to the current PHY speed/duplex
++ * settings.
++ */
++ if(hw->mac_type >= e1000_82544)
++ e1000_config_collision_dist(hw);
++ else {
++ if((ret_val = e1000_config_mac_to_phy(hw))) {
++ DEBUGOUT("Error configuring MAC to PHY settings\n");
++ return ret_val;
++ }
++ }
++
++ /* Configure Flow Control now that Auto-Neg has completed. First, we
++ * need to restore the desired flow control settings because we may
++ * have had to re-autoneg with a different link partner.
++ */
++ if((ret_val = e1000_config_fc_after_link_up(hw))) {
++ DEBUGOUT("Error configuring flow control\n");
++ return ret_val;
++ }
++
++ /* At this point we know that we are on copper and we have
++ * auto-negotiated link. These are conditions for checking the link
++ * parter capability register. We use the link partner capability to
++ * determine if TBI Compatibility needs to be turned on or off. If
++ * the link partner advertises any speed in addition to Gigabit, then
++ * we assume that they are GMII-based, and TBI compatibility is not
++ * needed. If no other speeds are advertised, we assume the link
++ * partner is TBI-based, and we turn on TBI Compatibility.
++ */
++ if(hw->tbi_compatibility_en) {
++ if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
++ &lp_capability)))
++ return ret_val;
++ if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
++ NWAY_LPAR_10T_FD_CAPS |
++ NWAY_LPAR_100TX_HD_CAPS |
++ NWAY_LPAR_100TX_FD_CAPS |
++ NWAY_LPAR_100T4_CAPS)) {
++ /* If our link partner advertises anything in addition to
++ * gigabit, we do not need to enable TBI compatibility.
++ */
++ if(hw->tbi_compatibility_on) {
++ /* If we previously were in the mode, turn it off. */
++ rctl = E1000_READ_REG(hw, RCTL);
++ rctl &= ~E1000_RCTL_SBP;
++ E1000_WRITE_REG(hw, RCTL, rctl);
++ hw->tbi_compatibility_on = FALSE;
++ }
++ } else {
++ /* If TBI compatibility is was previously off, turn it on. For
++ * compatibility with a TBI link partner, we will store bad
++ * packets. Some frames have an additional byte on the end and
++ * will look like CRC errors to to the hardware.
++ */
++ if(!hw->tbi_compatibility_on) {
++ hw->tbi_compatibility_on = TRUE;
++ rctl = E1000_READ_REG(hw, RCTL);
++ rctl |= E1000_RCTL_SBP;
++ E1000_WRITE_REG(hw, RCTL, rctl);
++ }
++ }
++ }
++ }
++ /* If we don't have link (auto-negotiation failed or link partner cannot
++ * auto-negotiate), the cable is plugged in (we have signal), and our
++ * link partner is not trying to auto-negotiate with us (we are receiving
++ * idles or data), we need to force link up. We also need to give
++ * auto-negotiation time to complete, in case the cable was just plugged
++ * in. The autoneg_failed flag does this.
++ */
++ else if((((hw->media_type == e1000_media_type_fiber) &&
++ ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
++ (hw->media_type == e1000_media_type_internal_serdes)) &&
++ (!(status & E1000_STATUS_LU)) &&
++ (!(rxcw & E1000_RXCW_C))) {
++ if(hw->autoneg_failed == 0) {
++ hw->autoneg_failed = 1;
++ return 0;
++ }
++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
++
++ /* Disable auto-negotiation in the TXCW register */
++ E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
++
++ /* Force link-up and also force full-duplex. */
++ ctrl = E1000_READ_REG(hw, CTRL);
++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++
++ /* Configure Flow Control after forcing link up. */
++ if((ret_val = e1000_config_fc_after_link_up(hw))) {
++ DEBUGOUT("Error configuring flow control\n");
++ return ret_val;
++ }
++ }
++ /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
++ * auto-negotiation in the TXCW register and disable forced link in the
++ * Device Control register in an attempt to auto-negotiate with our link
++ * partner.
++ */
++ else if(((hw->media_type == e1000_media_type_fiber) ||
++ (hw->media_type == e1000_media_type_internal_serdes)) &&
++ (ctrl & E1000_CTRL_SLU) &&
++ (rxcw & E1000_RXCW_C)) {
++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
++ E1000_WRITE_REG(hw, TXCW, hw->txcw);
++ E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
++ }
++#if 0
++ /* If we force link for non-auto-negotiation switch, check link status
++ * based on MAC synchronization for internal serdes media type.
++ */
++ else if((hw->media_type == e1000_media_type_internal_serdes) &&
++ !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
++ /* SYNCH bit and IV bit are sticky. */
++ udelay(10);
++ if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
++ if(!(rxcw & E1000_RXCW_IV)) {
++ hw->serdes_link_down = FALSE;
++ DEBUGOUT("SERDES: Link is up.\n");
++ }
++ } else {
++ hw->serdes_link_down = TRUE;
++ DEBUGOUT("SERDES: Link is down.\n");
++ }
++ }
++#endif
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++ * Detects the current speed and duplex settings of the hardware.
++ *
++ * hw - Struct containing variables accessed by shared code
++ * speed - Speed of the connection
++ * duplex - Duplex setting of the connection
++ *****************************************************************************/
++static void
++e1000_get_speed_and_duplex(struct e1000_hw *hw,
++ uint16_t *speed,
++ uint16_t *duplex)
++{
++ uint32_t status;
++
++ DEBUGFUNC("e1000_get_speed_and_duplex");
++
++ if(hw->mac_type >= e1000_82543) {
++ status = E1000_READ_REG(hw, STATUS);
++ if(status & E1000_STATUS_SPEED_1000) {
++ *speed = SPEED_1000;
++ DEBUGOUT("1000 Mbs, ");
++ } else if(status & E1000_STATUS_SPEED_100) {
++ *speed = SPEED_100;
++ DEBUGOUT("100 Mbs, ");
++ } else {
++ *speed = SPEED_10;
++ DEBUGOUT("10 Mbs, ");
++ }
++
++ if(status & E1000_STATUS_FD) {
++ *duplex = FULL_DUPLEX;
++ DEBUGOUT("Full Duplex\r\n");
++ } else {
++ *duplex = HALF_DUPLEX;
++ DEBUGOUT(" Half Duplex\r\n");
++ }
++ } else {
++ DEBUGOUT("1000 Mbs, Full Duplex\r\n");
++ *speed = SPEED_1000;
++ *duplex = FULL_DUPLEX;
++ }
++}
++
++/******************************************************************************
++* Blocks until autoneg completes or times out (~4.5 seconds)
++*
++* hw - Struct containing variables accessed by shared code
++******************************************************************************/
++static int
++e1000_wait_autoneg(struct e1000_hw *hw)
++{
++ int32_t ret_val;
++ uint16_t i;
++ uint16_t phy_data;
++
++ DEBUGFUNC("e1000_wait_autoneg");
++ DEBUGOUT("Waiting for Auto-Neg to complete.\n");
++
++ /* We will wait for autoneg to complete or 4.5 seconds to expire. */
++ for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
++ /* Read the MII Status Register and wait for Auto-Neg
++ * Complete bit to be set.
++ */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
++ return ret_val;
++ if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
++ return ret_val;
++ if(phy_data & MII_SR_AUTONEG_COMPLETE) {
++ DEBUGOUT("Auto-Neg complete.\n");
++ return E1000_SUCCESS;
++ }
++ mdelay(100);
++ }
++ DEBUGOUT("Auto-Neg timedout.\n");
++ return -E1000_ERR_TIMEOUT;
++}
++
++/******************************************************************************
++* Raises the Management Data Clock
++*
++* hw - Struct containing variables accessed by shared code
++* ctrl - Device control register's current value
++******************************************************************************/
++static void
++e1000_raise_mdi_clk(struct e1000_hw *hw,
++ uint32_t *ctrl)
++{
++ /* Raise the clock input to the Management Data Clock (by setting the MDC
++ * bit), and then delay 10 microseconds.
++ */
++ E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
++ E1000_WRITE_FLUSH(hw);
++ udelay(10);
++}
++
++/******************************************************************************
++* Lowers the Management Data Clock
++*
++* hw - Struct containing variables accessed by shared code
++* ctrl - Device control register's current value
++******************************************************************************/
++static void
++e1000_lower_mdi_clk(struct e1000_hw *hw,
++ uint32_t *ctrl)
++{
++ /* Lower the clock input to the Management Data Clock (by clearing the MDC
++ * bit), and then delay 10 microseconds.
++ */
++ E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
++ E1000_WRITE_FLUSH(hw);
++ udelay(10);
++}
++
++/******************************************************************************
++* Shifts data bits out to the PHY
++*
++* hw - Struct containing variables accessed by shared code
++* data - Data to send out to the PHY
++* count - Number of bits to shift out
++*
++* Bits are shifted out in MSB to LSB order.
++******************************************************************************/
++static void
++e1000_shift_out_mdi_bits(struct e1000_hw *hw,
++ uint32_t data,
++ uint16_t count)
++{
++ uint32_t ctrl;
++ uint32_t mask;
++
++ /* We need to shift "count" number of bits out to the PHY. So, the value
++ * in the "data" parameter will be shifted out to the PHY one bit at a
++ * time. In order to do this, "data" must be broken down into bits.
++ */
++ mask = 0x01;
++ mask <<= (count - 1);
++
++ ctrl = E1000_READ_REG(hw, CTRL);
++
++ /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
++ ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
++
++ while(mask) {
++ /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
++ * then raising and lowering the Management Data Clock. A "0" is
++ * shifted out to the PHY by setting the MDIO bit to "0" and then
++ * raising and lowering the clock.
++ */
++ if(data & mask) ctrl |= E1000_CTRL_MDIO;
++ else ctrl &= ~E1000_CTRL_MDIO;
++
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ E1000_WRITE_FLUSH(hw);
++
++ udelay(10);
++
++ e1000_raise_mdi_clk(hw, &ctrl);
++ e1000_lower_mdi_clk(hw, &ctrl);
++
++ mask = mask >> 1;
++ }
++}
++
++/******************************************************************************
++* Shifts data bits in from the PHY
++*
++* hw - Struct containing variables accessed by shared code
++*
++* Bits are shifted in in MSB to LSB order.
++******************************************************************************/
++static uint16_t
++e1000_shift_in_mdi_bits(struct e1000_hw *hw)
++{
++ uint32_t ctrl;
++ uint16_t data = 0;
++ uint8_t i;
++
++ /* In order to read a register from the PHY, we need to shift in a total
++ * of 18 bits from the PHY. The first two bit (turnaround) times are used
++ * to avoid contention on the MDIO pin when a read operation is performed.
++ * These two bits are ignored by us and thrown away. Bits are "shifted in"
++ * by raising the input to the Management Data Clock (setting the MDC bit),
++ * and then reading the value of the MDIO bit.
++ */
++ ctrl = E1000_READ_REG(hw, CTRL);
++
++ /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
++ ctrl &= ~E1000_CTRL_MDIO_DIR;
++ ctrl &= ~E1000_CTRL_MDIO;
++
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ E1000_WRITE_FLUSH(hw);
++
++ /* Raise and Lower the clock before reading in the data. This accounts for
++ * the turnaround bits. The first clock occurred when we clocked out the
++ * last bit of the Register Address.
++ */
++ e1000_raise_mdi_clk(hw, &ctrl);
++ e1000_lower_mdi_clk(hw, &ctrl);
++
++ for(data = 0, i = 0; i < 16; i++) {
++ data = data << 1;
++ e1000_raise_mdi_clk(hw, &ctrl);
++ ctrl = E1000_READ_REG(hw, CTRL);
++ /* Check to see if we shifted in a "1". */
++ if(ctrl & E1000_CTRL_MDIO) data |= 1;
++ e1000_lower_mdi_clk(hw, &ctrl);
++ }
++
++ e1000_raise_mdi_clk(hw, &ctrl);
++ e1000_lower_mdi_clk(hw, &ctrl);
++
++ return data;
++}
++
++/*****************************************************************************
++* Reads the value from a PHY register, if the value is on a specific non zero
++* page, sets the page first.
++*
++* hw - Struct containing variables accessed by shared code
++* reg_addr - address of the PHY register to read
++******************************************************************************/
++static int
++e1000_read_phy_reg(struct e1000_hw *hw,
++ uint32_t reg_addr,
++ uint16_t *phy_data)
++{
++ uint32_t ret_val;
++
++ DEBUGFUNC("e1000_read_phy_reg");
++
++ if(hw->phy_type == e1000_phy_igp &&
++ (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
++ if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
++ (uint16_t)reg_addr)))
++ return ret_val;
++ }
++
++ ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
++ phy_data);
++
++ return ret_val;
++}
++
++static int
++e1000_read_phy_reg_ex(struct e1000_hw *hw,
++ uint32_t reg_addr,
++ uint16_t *phy_data)
++{
++ uint32_t i;
++ uint32_t mdic = 0;
++ const uint32_t phy_addr = 1;
++
++ DEBUGFUNC("e1000_read_phy_reg_ex");
++
++ if(reg_addr > MAX_PHY_REG_ADDRESS) {
++ DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
++ return -E1000_ERR_PARAM;
++ }
++
++ if(hw->mac_type > e1000_82543) {
++ /* Set up Op-code, Phy Address, and register address in the MDI
++ * Control register. The MAC will take care of interfacing with the
++ * PHY to retrieve the desired data.
++ */
++ mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
++ (phy_addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_READ));
++
++ E1000_WRITE_REG(hw, MDIC, mdic);
++
++ /* Poll the ready bit to see if the MDI read completed */
++ for(i = 0; i < 64; i++) {
++ udelay(50);
++ mdic = E1000_READ_REG(hw, MDIC);
++ if(mdic & E1000_MDIC_READY) break;
++ }
++ if(!(mdic & E1000_MDIC_READY)) {
++ DEBUGOUT("MDI Read did not complete\n");
++ return -E1000_ERR_PHY;
++ }
++ if(mdic & E1000_MDIC_ERROR) {
++ DEBUGOUT("MDI Error\n");
++ return -E1000_ERR_PHY;
++ }
++ *phy_data = (uint16_t) mdic;
++ } else {
++ /* We must first send a preamble through the MDIO pin to signal the
++ * beginning of an MII instruction. This is done by sending 32
++ * consecutive "1" bits.
++ */
++ e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
++
++ /* Now combine the next few fields that are required for a read
++ * operation. We use this method instead of calling the
++ * e1000_shift_out_mdi_bits routine five different times. The format of
++ * a MII read instruction consists of a shift out of 14 bits and is
++ * defined as follows:
++ * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
++ * followed by a shift in of 18 bits. This first two bits shifted in
++ * are TurnAround bits used to avoid contention on the MDIO pin when a
++ * READ operation is performed. These two bits are thrown away
++ * followed by a shift in of 16 bits which contains the desired data.
++ */
++ mdic = ((reg_addr) | (phy_addr << 5) |
++ (PHY_OP_READ << 10) | (PHY_SOF << 12));
++
++ e1000_shift_out_mdi_bits(hw, mdic, 14);
++
++ /* Now that we've shifted out the read command to the MII, we need to
++ * "shift in" the 16-bit value (18 total bits) of the requested PHY
++ * register address.
++ */
++ *phy_data = e1000_shift_in_mdi_bits(hw);
++ }
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++* Writes a value to a PHY register
++*
++* hw - Struct containing variables accessed by shared code
++* reg_addr - address of the PHY register to write
++* data - data to write to the PHY
++******************************************************************************/
++static int
++e1000_write_phy_reg(struct e1000_hw *hw,
++ uint32_t reg_addr,
++ uint16_t phy_data)
++{
++ uint32_t ret_val;
++
++ DEBUGFUNC("e1000_write_phy_reg");
++
++ if(hw->phy_type == e1000_phy_igp &&
++ (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
++ if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
++ (uint16_t)reg_addr)))
++ return ret_val;
++ }
++
++ ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
++ phy_data);
++
++ return ret_val;
++}
++
++static int
++e1000_write_phy_reg_ex(struct e1000_hw *hw,
++ uint32_t reg_addr,
++ uint16_t phy_data)
++{
++ uint32_t i;
++ uint32_t mdic = 0;
++ const uint32_t phy_addr = 1;
++
++ DEBUGFUNC("e1000_write_phy_reg_ex");
++
++ if(reg_addr > MAX_PHY_REG_ADDRESS) {
++ DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
++ return -E1000_ERR_PARAM;
++ }
++
++ if(hw->mac_type > e1000_82543) {
++ /* Set up Op-code, Phy Address, register address, and data intended
++ * for the PHY register in the MDI Control register. The MAC will take
++ * care of interfacing with the PHY to send the desired data.
++ */
++ mdic = (((uint32_t) phy_data) |
++ (reg_addr << E1000_MDIC_REG_SHIFT) |
++ (phy_addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_WRITE));
++
++ E1000_WRITE_REG(hw, MDIC, mdic);
++
++ /* Poll the ready bit to see if the MDI read completed */
++ for(i = 0; i < 640; i++) {
++ udelay(5);
++ mdic = E1000_READ_REG(hw, MDIC);
++ if(mdic & E1000_MDIC_READY) break;
++ }
++ if(!(mdic & E1000_MDIC_READY)) {
++ DEBUGOUT("MDI Write did not complete\n");
++ return -E1000_ERR_PHY;
++ }
++ } else {
++ /* We'll need to use the SW defined pins to shift the write command
++ * out to the PHY. We first send a preamble to the PHY to signal the
++ * beginning of the MII instruction. This is done by sending 32
++ * consecutive "1" bits.
++ */
++ e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
++
++ /* Now combine the remaining required fields that will indicate a
++ * write operation. We use this method instead of calling the
++ * e1000_shift_out_mdi_bits routine for each field in the command. The
++ * format of a MII write instruction is as follows:
++ * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
++ */
++ mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
++ (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
++ mdic <<= 16;
++ mdic |= (uint32_t) phy_data;
++
++ e1000_shift_out_mdi_bits(hw, mdic, 32);
++ }
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++* Returns the PHY to the power-on reset state
++*
++* hw - Struct containing variables accessed by shared code
++******************************************************************************/
++static void
++e1000_phy_hw_reset(struct e1000_hw *hw)
++{
++ uint32_t ctrl, ctrl_ext;
++
++ DEBUGFUNC("e1000_phy_hw_reset");
++
++ DEBUGOUT("Resetting Phy...\n");
++
++ if(hw->mac_type > e1000_82543) {
++ /* Read the device control register and assert the E1000_CTRL_PHY_RST
++ * bit. Then, take it out of reset.
++ */
++ ctrl = E1000_READ_REG(hw, CTRL);
++ E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
++ E1000_WRITE_FLUSH(hw);
++ mdelay(10);
++ E1000_WRITE_REG(hw, CTRL, ctrl);
++ E1000_WRITE_FLUSH(hw);
++ } else {
++ /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
++ * bit to put the PHY into reset. Then, take it out of reset.
++ */
++ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
++ ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
++ ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
++ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
++ E1000_WRITE_FLUSH(hw);
++ mdelay(10);
++ ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
++ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
++ E1000_WRITE_FLUSH(hw);
++ }
++ udelay(150);
++}
++
++/******************************************************************************
++* Resets the PHY
++*
++* hw - Struct containing variables accessed by shared code
++*
++* Sets bit 15 of the MII Control regiser
++******************************************************************************/
++static int
++e1000_phy_reset(struct e1000_hw *hw)
++{
++ int32_t ret_val;
++ uint16_t phy_data;
++
++ DEBUGFUNC("e1000_phy_reset");
++
++ if(hw->mac_type != e1000_82541_rev_2) {
++ if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
++ return ret_val;
++
++ phy_data |= MII_CR_RESET;
++ if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
++ return ret_val;
++
++ udelay(1);
++ } else e1000_phy_hw_reset(hw);
++
++ if(hw->phy_type == e1000_phy_igp)
++ e1000_phy_init_script(hw);
++
++ return E1000_SUCCESS;
++}
++
++/******************************************************************************
++* Probes the expected PHY address for known PHY IDs
++*
++* hw - Struct containing variables accessed by shared code
++******************************************************************************/
++static int
++e1000_detect_gig_phy(struct e1000_hw *hw)
++{
++ int32_t phy_init_status, ret_val;
++ uint16_t phy_id_high, phy_id_low;
++ boolean_t match = FALSE;
++
++ DEBUGFUNC("e1000_detect_gig_phy");
++
++ /* Read the PHY ID Registers to identify which PHY is onboard. */
++ if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
++ return ret_val;
++
++ hw->phy_id = (uint32_t) (phy_id_high << 16);
++ udelay(20);
++ if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
++ return ret_val;
++
++ hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
++#ifdef LINUX_DRIVER
++ hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
++#endif
++
++ switch(hw->mac_type) {
++ case e1000_82543:
++ if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
++ break;
++ case e1000_82544:
++ if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
++ break;
++ case e1000_82540:
++ case e1000_82545:
++ case e1000_82545_rev_3:
++ case e1000_82546:
++ case e1000_82546_rev_3:
++ if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
++ break;
++ case e1000_82541:
++ case e1000_82541_rev_2:
++ case e1000_82547:
++ case e1000_82547_rev_2:
++ if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
++ break;
++ default:
++ DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
++ return -E1000_ERR_CONFIG;
++ }
++ phy_init_status = e1000_set_phy_type(hw);
++
++ if ((match) && (phy_init_status == E1000_SUCCESS)) {
++ DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
++ return E1000_SUCCESS;
++ }
++ DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
++ return -E1000_ERR_PHY;
++}
++
++/******************************************************************************
++ * Sets up eeprom variables in the hw struct. Must be called after mac_type
++ * is configured.
++ *
++ * hw - Struct containing variables accessed by shared code
++ *****************************************************************************/
++static void
++e1000_init_eeprom_params(struct e1000_hw *hw)
++{
++ struct e1000_eeprom_info *eeprom = &hw->eeprom;
++ uint32_t eecd = E1000_READ_REG(hw, EECD);
++ uint16_t eeprom_size;
++
++ DEBUGFUNC("e1000_init_eeprom_params");
++
++ switch (hw->mac_type) {
++ case e1000_82542_rev2_0:
++ case e1000_82542_rev2_1:
++ case e1000_82543:
++ case e1000_82544:
++ eeprom->type = e1000_eeprom_microwire;
++ eeprom->word_size = 64;
++ eeprom->opcode_bits = 3;
++ eeprom->address_bits = 6;
++ eeprom->delay_usec = 50;
++ break;
++ case e1000_82540:
++ case e1000_82545:
++ case e1000_82545_rev_3:
++ case e1000_82546:
++ case e1000_82546_rev_3:
++ eeprom->type = e1000_eeprom_microwire;
++ eeprom->opcode_bits = 3;
++ eeprom->delay_usec = 50;
++ if(eecd & E1000_EECD_SIZE) {
++ eeprom->word_size = 256;
++ eeprom->address_bits = 8;
++ } else {
++ eeprom->word_size = 64;
++ eeprom->address_bits = 6;
++ }
++ break;
++ case e1000_82541:
++ case e1000_82541_rev_2:
++ case e1000_82547:
++ case e1000_82547_rev_2:
++ if (eecd & E1000_EECD_TYPE) {
++ eeprom->type = e1000_eeprom_spi;
++ if (eecd & E1000_EECD_ADDR_BITS) {
++ eeprom->page_size = 32;
++ eeprom->address_bits = 16;
++ } else {
++ eeprom->page_size = 8;
++ eeprom->address_bits = 8;
++ }
++ } else {
++ eeprom->type = e1000_eeprom_microwire;
++ eeprom->opcode_bits = 3;
++ eeprom->delay_usec = 50;
++ if (eecd & E1000_EECD_ADDR_BITS) {
++ eeprom->word_size = 256;
++ eeprom->address_bits = 8;
++ } else {
++ eeprom->word_size = 64;
++ eeprom->address_bits = 6;
++ }
++ }
++ break;
++ default:
++ eeprom->type = e1000_eeprom_spi;
++ if (eecd & E1000_EECD_ADDR_BITS) {
++ eeprom->page_size = 32;
++ eeprom->address_bits = 16;
++ } else {
++ eeprom->page_size = 8;
++ eeprom->address_bits = 8;
++ }
++ break;
++ }
++
++ if (eeprom->type == e1000_eeprom_spi) {
++ eeprom->opcode_bits = 8;
++ eeprom->delay_usec = 1;
++ eeprom->word_size = 64;
++ if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
++ eeprom_size &= EEPROM_SIZE_MASK;
++
++ switch (eeprom_size) {
++ case EEPROM_SIZE_16KB:
++ eeprom->word_size = 8192;
++ break;
++ case EEPROM_SIZE_8KB:
++ eeprom->word_size = 4096;
++ break;
++ case EEPROM_SIZE_4KB:
++ eeprom->word_size = 2048;
++ break;
++ case EEPROM_SIZE_2KB:
++ eeprom->word_size = 1024;
++ break;
++ case EEPROM_SIZE_1KB:
++ eeprom->word_size = 512;
++ break;
++ case EEPROM_SIZE_512B:
++ eeprom->word_size = 256;
++ break;
++ case EEPROM_SIZE_128B:
++ default:
++ break;
++ }
++ }
++ }
++}
++
++/**
++ * e1000_reset - Reset the adapter
++ */
++
++static int
++e1000_reset(struct e1000_hw *hw)
++{
++ uint32_t pba;
++ /* Repartition Pba for greater than 9k mtu
++ * To take effect CTRL.RST is required.
++ */
++
++ if(hw->mac_type < e1000_82547) {
++ pba = E1000_PBA_48K;
++ } else {
++ pba = E1000_PBA_30K;
++ }
++ E1000_WRITE_REG(hw, PBA, pba);
++
++ /* flow control settings */
++#if 0
++ hw->fc_high_water = FC_DEFAULT_HI_THRESH;
++ hw->fc_low_water = FC_DEFAULT_LO_THRESH;
++ hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
++ hw->fc_send_xon = 1;
++ hw->fc = hw->original_fc;
++#endif
++
++ e1000_reset_hw(hw);
++ if(hw->mac_type >= e1000_82544)
++ E1000_WRITE_REG(hw, WUC, 0);
++ return e1000_init_hw(hw);
++}
++
++/**
++ * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
++ * @adapter: board private structure to initialize
++ *
++ * e1000_sw_init initializes the Adapter private data structure.
++ * Fields are initialized based on PCI device information and
++ * OS network device settings (MTU size).
++ **/
++
++static int
++e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
++{
++ int result;
++
++ /* PCI config space info */
++ pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
++ pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
++ pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
++#if 0
++ pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
++ &hw->subsystem_vendor_id);
++ pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
++#endif
++
++ pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
++
++ /* identify the MAC */
++
++ result = e1000_set_mac_type(hw);
++ if (result) {
++ E1000_ERR("Unknown MAC Type\n");
++ return result;
++ }
++
++ /* initialize eeprom parameters */
++
++ e1000_init_eeprom_params(hw);
++
++#if 0
++ if((hw->mac_type == e1000_82541) ||
++ (hw->mac_type == e1000_82547) ||
++ (hw->mac_type == e1000_82541_rev_2) ||
++ (hw->mac_type == e1000_82547_rev_2))
++ hw->phy_init_script = 1;
++#endif
++
++ e1000_set_media_type(hw);
++
++#if 0
++ if(hw->mac_type < e1000_82543)
++ hw->report_tx_early = 0;
++ else
++ hw->report_tx_early = 1;
++
++ hw->wait_autoneg_complete = FALSE;
++#endif
++ hw->tbi_compatibility_en = TRUE;
++#if 0
++ hw->adaptive_ifs = TRUE;
++
++ /* Copper options */
++
++ if(hw->media_type == e1000_media_type_copper) {
++ hw->mdix = AUTO_ALL_MODES;
++ hw->disable_polarity_correction = FALSE;
++ hw->master_slave = E1000_MASTER_SLAVE;
++ }
++#endif
++ return E1000_SUCCESS;
++}
++
++static void fill_rx (void)
++{
++ struct e1000_rx_desc *rd;
++ rx_last = rx_tail;
++ rd = rx_base + rx_tail;
++ rx_tail = (rx_tail + 1) % 8;
++ memset (rd, 0, 16);
++ rd->buffer_addr = virt_to_bus(&packet);
++ E1000_WRITE_REG (&hw, RDT, rx_tail);
++}
++
++static void init_descriptor (void)
++{
++ unsigned long ptr;
++ unsigned long tctl;
++
++ ptr = virt_to_phys(tx_pool);
++ if (ptr & 0xf)
++ ptr = (ptr + 0x10) & (~0xf);
++
++ tx_base = phys_to_virt(ptr);
++
++ E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
++ E1000_WRITE_REG (&hw, TDBAH, 0);
++ E1000_WRITE_REG (&hw, TDLEN, 128);
++
++ /* Setup the HW Tx Head and Tail descriptor pointers */
++
++ E1000_WRITE_REG (&hw, TDH, 0);
++ E1000_WRITE_REG (&hw, TDT, 0);
++ tx_tail = 0;
++
++ /* Program the Transmit Control Register */
++
++#ifdef LINUX_DRIVER_TCTL
++ tctl = E1000_READ_REG(&hw, TCTL);
++
++ tctl &= ~E1000_TCTL_CT;
++ tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
++ (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
++#else
++ tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
++ (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
++ (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
++#endif
++
++ E1000_WRITE_REG (&hw, TCTL, tctl);
++
++ e1000_config_collision_dist(&hw);
++
++
++ rx_tail = 0;
++ /* disable receive */
++ E1000_WRITE_REG (&hw, RCTL, 0);
++ ptr = virt_to_phys(rx_pool);
++ if (ptr & 0xf)
++ ptr = (ptr + 0x10) & (~0xf);
++ rx_base = phys_to_virt(ptr);
++
++ /* Setup the Base and Length of the Rx Descriptor Ring */
++
++ E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
++ E1000_WRITE_REG (&hw, RDBAH, 0);
++
++ E1000_WRITE_REG (&hw, RDLEN, 128);
++
++ /* Setup the HW Rx Head and Tail Descriptor Pointers */
++ E1000_WRITE_REG (&hw, RDH, 0);
++ E1000_WRITE_REG (&hw, RDT, 0);
++
++ E1000_WRITE_REG (&hw, RCTL,
++ E1000_RCTL_EN |
++ E1000_RCTL_BAM |
++ E1000_RCTL_SZ_2048 |
++ E1000_RCTL_MPE);
++ fill_rx();
++}
++
++
++
++/**************************************************************************
++POLL - Wait for a frame
++***************************************************************************/
++static int
++e1000_poll (struct nic *nic, int retrieve)
++{
++ /* return true if there's an ethernet packet ready to read */
++ /* nic->packet should contain data on return */
++ /* nic->packetlen should contain length of data */
++ struct e1000_rx_desc *rd;
++
++ rd = rx_base + rx_last;
++ if (!rd->status & E1000_RXD_STAT_DD)
++ return 0;
++
++ if ( ! retrieve ) return 1;
++
++ // printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
++ memcpy (nic->packet, packet, rd->length);
++ nic->packetlen = rd->length;
++ fill_rx ();
++ return 1;
++}
++
++/**************************************************************************
++TRANSMIT - Transmit a frame
++***************************************************************************/
++static void
++e1000_transmit (struct nic *nic, const char *d, /* Destination */
++ unsigned int type, /* Type */
++ unsigned int size, /* size */
++ const char *p) /* Packet */
++{
++ /* send the packet to destination */
++ struct eth_hdr {
++ unsigned char dst_addr[ETH_ALEN];
++ unsigned char src_addr[ETH_ALEN];
++ unsigned short type;
++ } hdr;
++ struct e1000_tx_desc *txhd; /* header */
++ struct e1000_tx_desc *txp; /* payload */
++ DEBUGFUNC("send");
++
++ memcpy (&hdr.dst_addr, d, ETH_ALEN);
++ memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
++
++ hdr.type = htons (type);
++ txhd = tx_base + tx_tail;
++ tx_tail = (tx_tail + 1) % 8;
++ txp = tx_base + tx_tail;
++ tx_tail = (tx_tail + 1) % 8;
++
++ txhd->buffer_addr = virt_to_bus (&hdr);
++ txhd->lower.data = sizeof (hdr);
++ txhd->upper.data = 0;
++
++ txp->buffer_addr = virt_to_bus(p);
++ txp->lower.data = E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | size;
++ txp->upper.data = 0;
++
++ E1000_WRITE_REG (&hw, TDT, tx_tail);
++ while (!(txp->upper.data & E1000_TXD_STAT_DD)) {
++ udelay(10); /* give the nic a chance to write to the register */
++ poll_interruptions();
++ }
++ DEBUGFUNC("send end");
++}
++
++
++/**************************************************************************
++DISABLE - Turn off ethernet interface
++***************************************************************************/
++static void e1000_disable (struct dev *dev __unused)
++{
++ /* Clear the transmit ring */
++ E1000_WRITE_REG (&hw, TDH, 0);
++ E1000_WRITE_REG (&hw, TDT, 0);
++
++ /* Clear the receive ring */
++ E1000_WRITE_REG (&hw, RDH, 0);
++ E1000_WRITE_REG (&hw, RDT, 0);
++
++ /* put the card in its initial state */
++ E1000_WRITE_REG (&hw, CTRL, E1000_CTRL_RST);
++
++ /* Turn off the ethernet interface */
++ E1000_WRITE_REG (&hw, RCTL, 0);
++ E1000_WRITE_REG (&hw, TCTL, 0);
++ mdelay (10);
++
++ /* Unmap my window to the device */
++ iounmap(hw.hw_addr);
++}
++
++/**************************************************************************
++IRQ - Enable, Disable, or Force interrupts
++***************************************************************************/
++static void e1000_irq(struct nic *nic __unused, irq_action_t action __unused)
++{
++ switch ( action ) {
++ case DISABLE :
++ break;
++ case ENABLE :
++ break;
++ case FORCE :
++ break;
++ }
++}
++
++#define IORESOURCE_IO 0x00000100 /* Resource type */
++#define BAR_0 0
++#define BAR_1 1
++#define BAR_5 5
++
++/**************************************************************************
++PROBE - Look for an adapter, this routine's visible to the outside
++You should omit the last argument struct pci_device * for a non-PCI NIC
++***************************************************************************/
++static int e1000_probe(struct dev *dev, struct pci_device *p)
++{
++ struct nic *nic = (struct nic *)dev;
++ unsigned long mmio_start, mmio_len;
++ int ret_val, i;
++
++ if (p == 0)
++ return 0;
++ /* Initialize hw with default values */
++ memset(&hw, 0, sizeof(hw));
++ hw.pdev = p;
++
++#if 1
++ /* Are these variables needed? */
++ hw.fc = e1000_fc_none;
++#if 0
++ hw.original_fc = e1000_fc_none;
++#endif
++ hw.autoneg_failed = 0;
++#if 0
++ hw.get_link_status = TRUE;
++#endif
++#endif
++
++ mmio_start = pci_bar_start(p, PCI_BASE_ADDRESS_0);
++ mmio_len = pci_bar_size(p, PCI_BASE_ADDRESS_0);
++ hw.hw_addr = ioremap(mmio_start, mmio_len);
++
++ for(i = BAR_1; i <= BAR_5; i++) {
++ if(pci_bar_size(p, i) == 0)
++ continue;
++ if(pci_find_capability(p, i) & IORESOURCE_IO) {
++ hw.io_base = pci_bar_start(p, i);
++ break;
++ }
++ }
++
++ adjust_pci_device(p);
++
++ nic->ioaddr = p->ioaddr & ~3;
++ nic->irqno = 0;
++
++ /* From Matt Hortman <mbhortman@acpthinclient.com> */
++ /* MAC and Phy settings */
++
++ /* setup the private structure */
++ if (e1000_sw_init(p, &hw) < 0) {
++ iounmap(hw.hw_addr);
++ return 0;
++ }
++
++ /* make sure the EEPROM is good */
++
++ if (e1000_validate_eeprom_checksum(&hw) < 0) {
++ printf ("The EEPROM Checksum Is Not Valid\n");
++ iounmap(hw.hw_addr);
++ return 0;
++ }
++
++ /* copy the MAC address out of the EEPROM */
++
++ e1000_read_mac_addr(&hw);
++ memcpy (nic->node_addr, hw.mac_addr, ETH_ALEN);
++
++ printf("Ethernet addr: %!\n", nic->node_addr);
++
++ /* reset the hardware with the new settings */
++
++ ret_val = e1000_reset(&hw);
++ if (ret_val < 0) {
++ if ((ret_val == -E1000_ERR_NOLINK) ||
++ (ret_val == -E1000_ERR_TIMEOUT)) {
++ E1000_ERR("Valid Link not detected\n");
++ } else {
++ E1000_ERR("Hardware Initialization Failed\n");
++ }
++ iounmap(hw.hw_addr);
++ return 0;
++ }
++ init_descriptor();
++
++ /* point to NIC specific routines */
++ dev->disable = e1000_disable;
++ nic->poll = e1000_poll;
++ nic->transmit = e1000_transmit;
++ nic->irq = e1000_irq;
++
++ return 1;
++}
++
++static struct pci_id e1000_nics[] = {
++PCI_ROM(0x8086, 0x1000, "e1000-82542", "Intel EtherExpressPro1000"),
++PCI_ROM(0x8086, 0x1001, "e1000-82543gc-fiber", "Intel EtherExpressPro1000 82543GC Fiber"),
++PCI_ROM(0x8086, 0x1004, "e1000-82543gc-copper", "Intel EtherExpressPro1000 82543GC Copper"),
++PCI_ROM(0x8086, 0x1008, "e1000-82544ei-copper", "Intel EtherExpressPro1000 82544EI Copper"),
++PCI_ROM(0x8086, 0x1009, "e1000-82544ei-fiber", "Intel EtherExpressPro1000 82544EI Fiber"),
++PCI_ROM(0x8086, 0x100C, "e1000-82544gc-copper", "Intel EtherExpressPro1000 82544GC Copper"),
++PCI_ROM(0x8086, 0x100D, "e1000-82544gc-lom", "Intel EtherExpressPro1000 82544GC LOM"),
++PCI_ROM(0x8086, 0x100E, "e1000-82540em", "Intel EtherExpressPro1000 82540EM"),
++PCI_ROM(0x8086, 0x100F, "e1000-82545em-copper", "Intel EtherExpressPro1000 82545EM Copper"),
++PCI_ROM(0x8086, 0x1010, "e1000-82546eb-copper", "Intel EtherExpressPro1000 82546EB Copper"),
++PCI_ROM(0x8086, 0x1011, "e1000-82545em-fiber", "Intel EtherExpressPro1000 82545EM Fiber"),
++PCI_ROM(0x8086, 0x1012, "e1000-82546eb-fiber", "Intel EtherExpressPro1000 82546EB Copper"),
++PCI_ROM(0x8086, 0x1013, "e1000-82541ei", "Intel EtherExpressPro1000 82541EI"),
++PCI_ROM(0x8086, 0x1015, "e1000-82540em-lom", "Intel EtherExpressPro1000 82540EM LOM"),
++PCI_ROM(0x8086, 0x1016, "e1000-82540ep-lom", "Intel EtherExpressPro1000 82540EP LOM"),
++PCI_ROM(0x8086, 0x1017, "e1000-82540ep", "Intel EtherExpressPro1000 82540EP"),
++PCI_ROM(0x8086, 0x1018, "e1000-82541ep", "Intel EtherExpressPro1000 82541EP"),
++PCI_ROM(0x8086, 0x1019, "e1000-82547ei", "Intel EtherExpressPro1000 82547EI"),
++PCI_ROM(0x8086, 0x101d, "e1000-82546eb-quad-copper", "Intel EtherExpressPro1000 82546EB Quad Copper"),
++PCI_ROM(0x8086, 0x101e, "e1000-82540ep-lp", "Intel EtherExpressPro1000 82540EP LP"),
++PCI_ROM(0x8086, 0x1026, "e1000-82545gm-copper", "Intel EtherExpressPro1000 82545GM Copper"),
++PCI_ROM(0x8086, 0x1027, "e1000-82545gm-fiber", "Intel EtherExpressPro1000 82545GM Fiber"),
++PCI_ROM(0x8086, 0x1028, "e1000-82545gm-serdes", "Intel EtherExpressPro1000 82545GM SERDES"),
++PCI_ROM(0x8086, 0x1075, "e1000-82547gi", "Intel EtherExpressPro1000 82547GI"),
++PCI_ROM(0x8086, 0x1076, "e1000-82541gi", "Intel EtherExpressPro1000 82541GI"),
++PCI_ROM(0x8086, 0x1077, "e1000-82541gi-mobile", "Intel EtherExpressPro1000 82541GI Mobile"),
++PCI_ROM(0x8086, 0x1078, "e1000-82541er", "Intel EtherExpressPro1000 82541ER"),
++PCI_ROM(0x8086, 0x1079, "e1000-82546gb-copper", "Intel EtherExpressPro1000 82546GB Copper"),
++PCI_ROM(0x8086, 0x107a, "e1000-82546gb-fiber", "Intel EtherExpressPro1000 82546GB Fiber"),
++PCI_ROM(0x8086, 0x107b, "e1000-82546gb-serdes", "Intel EtherExpressPro1000 82546GB SERDES"),
++};
++
++struct pci_driver e1000_driver = {
++ .type = NIC_DRIVER,
++ .name = "E1000",
++ .probe = e1000_probe,
++ .ids = e1000_nics,
++ .id_count = sizeof(e1000_nics)/sizeof(e1000_nics[0]),
++ .class = 0,
++};
+diff -Naur grub-0.97.orig/netboot/e1000_hw.h grub-0.97/netboot/e1000_hw.h
+--- grub-0.97.orig/netboot/e1000_hw.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/e1000_hw.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,2058 @@
++/*******************************************************************************
++
++
++ Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published by the Free
++ Software Foundation; either version 2 of the License, or (at your option)
++ any later version.
++
++ This program is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc., 59
++ Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++
++ The full GNU General Public License is included in this distribution in the
++ file called LICENSE.
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++/* e1000_hw.h
++ * Structures, enums, and macros for the MAC
++ */
++
++#ifndef _E1000_HW_H_
++#define _E1000_HW_H_
++
++/* Forward declarations of structures used by the shared code */
++struct e1000_hw;
++struct e1000_hw_stats;
++
++/* Enumerated types specific to the e1000 hardware */
++/* Media Access Controlers */
++typedef enum {
++ e1000_undefined = 0,
++ e1000_82542_rev2_0,
++ e1000_82542_rev2_1,
++ e1000_82543,
++ e1000_82544,
++ e1000_82540,
++ e1000_82545,
++ e1000_82545_rev_3,
++ e1000_82546,
++ e1000_82546_rev_3,
++ e1000_82541,
++ e1000_82541_rev_2,
++ e1000_82547,
++ e1000_82547_rev_2,
++ e1000_num_macs
++} e1000_mac_type;
++
++typedef enum {
++ e1000_eeprom_uninitialized = 0,
++ e1000_eeprom_spi,
++ e1000_eeprom_microwire,
++ e1000_num_eeprom_types
++} e1000_eeprom_type;
++
++/* Media Types */
++typedef enum {
++ e1000_media_type_copper = 0,
++ e1000_media_type_fiber = 1,
++ e1000_media_type_internal_serdes = 2,
++ e1000_num_media_types
++} e1000_media_type;
++
++typedef enum {
++ e1000_10_half = 0,
++ e1000_10_full = 1,
++ e1000_100_half = 2,
++ e1000_100_full = 3
++} e1000_speed_duplex_type;
++
++/* Flow Control Settings */
++typedef enum {
++ e1000_fc_none = 0,
++ e1000_fc_rx_pause = 1,
++ e1000_fc_tx_pause = 2,
++ e1000_fc_full = 3,
++ e1000_fc_default = 0xFF
++} e1000_fc_type;
++
++/* PCI bus types */
++typedef enum {
++ e1000_bus_type_unknown = 0,
++ e1000_bus_type_pci,
++ e1000_bus_type_pcix,
++ e1000_bus_type_reserved
++} e1000_bus_type;
++
++/* PCI bus speeds */
++typedef enum {
++ e1000_bus_speed_unknown = 0,
++ e1000_bus_speed_33,
++ e1000_bus_speed_66,
++ e1000_bus_speed_100,
++ e1000_bus_speed_120,
++ e1000_bus_speed_133,
++ e1000_bus_speed_reserved
++} e1000_bus_speed;
++
++/* PCI bus widths */
++typedef enum {
++ e1000_bus_width_unknown = 0,
++ e1000_bus_width_32,
++ e1000_bus_width_64,
++ e1000_bus_width_reserved
++} e1000_bus_width;
++
++/* PHY status info structure and supporting enums */
++typedef enum {
++ e1000_cable_length_50 = 0,
++ e1000_cable_length_50_80,
++ e1000_cable_length_80_110,
++ e1000_cable_length_110_140,
++ e1000_cable_length_140,
++ e1000_cable_length_undefined = 0xFF
++} e1000_cable_length;
++
++typedef enum {
++ e1000_igp_cable_length_10 = 10,
++ e1000_igp_cable_length_20 = 20,
++ e1000_igp_cable_length_30 = 30,
++ e1000_igp_cable_length_40 = 40,
++ e1000_igp_cable_length_50 = 50,
++ e1000_igp_cable_length_60 = 60,
++ e1000_igp_cable_length_70 = 70,
++ e1000_igp_cable_length_80 = 80,
++ e1000_igp_cable_length_90 = 90,
++ e1000_igp_cable_length_100 = 100,
++ e1000_igp_cable_length_110 = 110,
++ e1000_igp_cable_length_120 = 120,
++ e1000_igp_cable_length_130 = 130,
++ e1000_igp_cable_length_140 = 140,
++ e1000_igp_cable_length_150 = 150,
++ e1000_igp_cable_length_160 = 160,
++ e1000_igp_cable_length_170 = 170,
++ e1000_igp_cable_length_180 = 180
++} e1000_igp_cable_length;
++
++typedef enum {
++ e1000_10bt_ext_dist_enable_normal = 0,
++ e1000_10bt_ext_dist_enable_lower,
++ e1000_10bt_ext_dist_enable_undefined = 0xFF
++} e1000_10bt_ext_dist_enable;
++
++typedef enum {
++ e1000_rev_polarity_normal = 0,
++ e1000_rev_polarity_reversed,
++ e1000_rev_polarity_undefined = 0xFF
++} e1000_rev_polarity;
++
++typedef enum {
++ e1000_downshift_normal = 0,
++ e1000_downshift_activated,
++ e1000_downshift_undefined = 0xFF
++} e1000_downshift;
++
++typedef enum {
++ e1000_polarity_reversal_enabled = 0,
++ e1000_polarity_reversal_disabled,
++ e1000_polarity_reversal_undefined = 0xFF
++} e1000_polarity_reversal;
++
++typedef enum {
++ e1000_auto_x_mode_manual_mdi = 0,
++ e1000_auto_x_mode_manual_mdix,
++ e1000_auto_x_mode_auto1,
++ e1000_auto_x_mode_auto2,
++ e1000_auto_x_mode_undefined = 0xFF
++} e1000_auto_x_mode;
++
++typedef enum {
++ e1000_1000t_rx_status_not_ok = 0,
++ e1000_1000t_rx_status_ok,
++ e1000_1000t_rx_status_undefined = 0xFF
++} e1000_1000t_rx_status;
++
++typedef enum {
++ e1000_phy_m88 = 0,
++ e1000_phy_igp,
++ e1000_phy_undefined = 0xFF
++} e1000_phy_type;
++
++typedef enum {
++ e1000_ms_hw_default = 0,
++ e1000_ms_force_master,
++ e1000_ms_force_slave,
++ e1000_ms_auto
++} e1000_ms_type;
++
++typedef enum {
++ e1000_ffe_config_enabled = 0,
++ e1000_ffe_config_active,
++ e1000_ffe_config_blocked
++} e1000_ffe_config;
++
++typedef enum {
++ e1000_dsp_config_disabled = 0,
++ e1000_dsp_config_enabled,
++ e1000_dsp_config_activated,
++ e1000_dsp_config_undefined = 0xFF
++} e1000_dsp_config;
++
++struct e1000_phy_info {
++ e1000_cable_length cable_length;
++ e1000_10bt_ext_dist_enable extended_10bt_distance;
++ e1000_rev_polarity cable_polarity;
++ e1000_downshift downshift;
++ e1000_polarity_reversal polarity_correction;
++ e1000_auto_x_mode mdix_mode;
++ e1000_1000t_rx_status local_rx;
++ e1000_1000t_rx_status remote_rx;
++};
++
++struct e1000_phy_stats {
++ uint32_t idle_errors;
++ uint32_t receive_errors;
++};
++
++struct e1000_eeprom_info {
++ e1000_eeprom_type type;
++ uint16_t word_size;
++ uint16_t opcode_bits;
++ uint16_t address_bits;
++ uint16_t delay_usec;
++ uint16_t page_size;
++};
++
++
++
++/* Error Codes */
++#define E1000_SUCCESS 0
++#define E1000_ERR_EEPROM 1
++#define E1000_ERR_PHY 2
++#define E1000_ERR_CONFIG 3
++#define E1000_ERR_PARAM 4
++#define E1000_ERR_MAC_TYPE 5
++#define E1000_ERR_PHY_TYPE 6
++#define E1000_ERR_NOLINK 7
++#define E1000_ERR_TIMEOUT 8
++
++#define E1000_READ_REG_IO(a, reg) \
++ e1000_read_reg_io((a), E1000_##reg)
++#define E1000_WRITE_REG_IO(a, reg, val) \
++ e1000_write_reg_io((a), E1000_##reg, val)
++
++/* PCI Device IDs */
++#define E1000_DEV_ID_82542 0x1000
++#define E1000_DEV_ID_82543GC_FIBER 0x1001
++#define E1000_DEV_ID_82543GC_COPPER 0x1004
++#define E1000_DEV_ID_82544EI_COPPER 0x1008
++#define E1000_DEV_ID_82544EI_FIBER 0x1009
++#define E1000_DEV_ID_82544GC_COPPER 0x100C
++#define E1000_DEV_ID_82544GC_LOM 0x100D
++#define E1000_DEV_ID_82540EM 0x100E
++#define E1000_DEV_ID_82540EM_LOM 0x1015
++#define E1000_DEV_ID_82540EP_LOM 0x1016
++#define E1000_DEV_ID_82540EP 0x1017
++#define E1000_DEV_ID_82540EP_LP 0x101E
++#define E1000_DEV_ID_82545EM_COPPER 0x100F
++#define E1000_DEV_ID_82545EM_FIBER 0x1011
++#define E1000_DEV_ID_82545GM_COPPER 0x1026
++#define E1000_DEV_ID_82545GM_FIBER 0x1027
++#define E1000_DEV_ID_82545GM_SERDES 0x1028
++#define E1000_DEV_ID_82546EB_COPPER 0x1010
++#define E1000_DEV_ID_82546EB_FIBER 0x1012
++#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
++#define E1000_DEV_ID_82541EI 0x1013
++#define E1000_DEV_ID_82541EI_MOBILE 0x1018
++#define E1000_DEV_ID_82541ER 0x1078
++#define E1000_DEV_ID_82547GI 0x1075
++#define E1000_DEV_ID_82541GI 0x1076
++#define E1000_DEV_ID_82541GI_MOBILE 0x1077
++#define E1000_DEV_ID_82546GB_COPPER 0x1079
++#define E1000_DEV_ID_82546GB_FIBER 0x107A
++#define E1000_DEV_ID_82546GB_SERDES 0x107B
++#define E1000_DEV_ID_82547EI 0x1019
++
++#define NODE_ADDRESS_SIZE 6
++#define ETH_LENGTH_OF_ADDRESS 6
++
++/* MAC decode size is 128K - This is the size of BAR0 */
++#define MAC_DECODE_SIZE (128 * 1024)
++
++#define E1000_82542_2_0_REV_ID 2
++#define E1000_82542_2_1_REV_ID 3
++
++#define SPEED_10 10
++#define SPEED_100 100
++#define SPEED_1000 1000
++#define HALF_DUPLEX 1
++#define FULL_DUPLEX 2
++
++/* The sizes (in bytes) of a ethernet packet */
++#define ENET_HEADER_SIZE 14
++#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
++#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
++#define ETHERNET_FCS_SIZE 4
++#define MAXIMUM_ETHERNET_PACKET_SIZE \
++ (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
++#define MINIMUM_ETHERNET_PACKET_SIZE \
++ (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
++#define CRC_LENGTH ETHERNET_FCS_SIZE
++#define MAX_JUMBO_FRAME_SIZE 0x3F00
++
++
++/* 802.1q VLAN Packet Sizes */
++#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
++
++/* Ethertype field values */
++#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
++#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
++#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
++
++/* Packet Header defines */
++#define IP_PROTOCOL_TCP 6
++#define IP_PROTOCOL_UDP 0x11
++
++/* This defines the bits that are set in the Interrupt Mask
++ * Set/Read Register. Each bit is documented below:
++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
++ * o RXSEQ = Receive Sequence Error
++ */
++#define POLL_IMS_ENABLE_MASK ( \
++ E1000_IMS_RXDMT0 | \
++ E1000_IMS_RXSEQ)
++
++/* This defines the bits that are set in the Interrupt Mask
++ * Set/Read Register. Each bit is documented below:
++ * o RXT0 = Receiver Timer Interrupt (ring 0)
++ * o TXDW = Transmit Descriptor Written Back
++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
++ * o RXSEQ = Receive Sequence Error
++ * o LSC = Link Status Change
++ */
++#define IMS_ENABLE_MASK ( \
++ E1000_IMS_RXT0 | \
++ E1000_IMS_TXDW | \
++ E1000_IMS_RXDMT0 | \
++ E1000_IMS_RXSEQ | \
++ E1000_IMS_LSC)
++
++/* Number of high/low register pairs in the RAR. The RAR (Receive Address
++ * Registers) holds the directed and multicast addresses that we monitor. We
++ * reserve one of these spots for our directed address, allowing us room for
++ * E1000_RAR_ENTRIES - 1 multicast addresses.
++ */
++#define E1000_RAR_ENTRIES 15
++
++#define MIN_NUMBER_OF_DESCRIPTORS 8
++#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
++
++/* Receive Descriptor */
++struct e1000_rx_desc {
++ uint64_t buffer_addr; /* Address of the descriptor's data buffer */
++ uint16_t length; /* Length of data DMAed into data buffer */
++ uint16_t csum; /* Packet checksum */
++ uint8_t status; /* Descriptor status */
++ uint8_t errors; /* Descriptor Errors */
++ uint16_t special;
++};
++
++/* Receive Decriptor bit definitions */
++#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
++#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
++#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
++#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
++#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
++#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
++#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
++#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
++#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
++#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
++#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
++#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
++#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
++#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
++#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
++#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
++#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
++#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
++#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
++
++/* mask to determine if packets should be dropped due to frame errors */
++#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
++ E1000_RXD_ERR_CE | \
++ E1000_RXD_ERR_SE | \
++ E1000_RXD_ERR_SEQ | \
++ E1000_RXD_ERR_CXE | \
++ E1000_RXD_ERR_RXE)
++
++/* Transmit Descriptor */
++struct e1000_tx_desc {
++ uint64_t buffer_addr; /* Address of the descriptor's data buffer */
++ union {
++ uint32_t data;
++ struct {
++ uint16_t length; /* Data buffer length */
++ uint8_t cso; /* Checksum offset */
++ uint8_t cmd; /* Descriptor control */
++ } flags;
++ } lower;
++ union {
++ uint32_t data;
++ struct {
++ uint8_t status; /* Descriptor status */
++ uint8_t css; /* Checksum start */
++ uint16_t special;
++ } fields;
++ } upper;
++};
++
++/* Transmit Descriptor bit definitions */
++#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
++#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
++#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
++#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
++#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
++#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
++#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
++#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
++#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
++#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
++#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
++#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
++#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
++#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
++#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
++#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
++#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
++#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
++#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
++#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
++
++/* Offload Context Descriptor */
++struct e1000_context_desc {
++ union {
++ uint32_t ip_config;
++ struct {
++ uint8_t ipcss; /* IP checksum start */
++ uint8_t ipcso; /* IP checksum offset */
++ uint16_t ipcse; /* IP checksum end */
++ } ip_fields;
++ } lower_setup;
++ union {
++ uint32_t tcp_config;
++ struct {
++ uint8_t tucss; /* TCP checksum start */
++ uint8_t tucso; /* TCP checksum offset */
++ uint16_t tucse; /* TCP checksum end */
++ } tcp_fields;
++ } upper_setup;
++ uint32_t cmd_and_length; /* */
++ union {
++ uint32_t data;
++ struct {
++ uint8_t status; /* Descriptor status */
++ uint8_t hdr_len; /* Header length */
++ uint16_t mss; /* Maximum segment size */
++ } fields;
++ } tcp_seg_setup;
++};
++
++/* Offload data descriptor */
++struct e1000_data_desc {
++ uint64_t buffer_addr; /* Address of the descriptor's buffer address */
++ union {
++ uint32_t data;
++ struct {
++ uint16_t length; /* Data buffer length */
++ uint8_t typ_len_ext; /* */
++ uint8_t cmd; /* */
++ } flags;
++ } lower;
++ union {
++ uint32_t data;
++ struct {
++ uint8_t status; /* Descriptor status */
++ uint8_t popts; /* Packet Options */
++ uint16_t special; /* */
++ } fields;
++ } upper;
++};
++
++/* Filters */
++#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
++#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
++#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
++
++
++/* Receive Address Register */
++struct e1000_rar {
++ volatile uint32_t low; /* receive address low */
++ volatile uint32_t high; /* receive address high */
++};
++
++/* Number of entries in the Multicast Table Array (MTA). */
++#define E1000_NUM_MTA_REGISTERS 128
++
++/* IPv4 Address Table Entry */
++struct e1000_ipv4_at_entry {
++ volatile uint32_t ipv4_addr; /* IP Address (RW) */
++ volatile uint32_t reserved;
++};
++
++/* Four wakeup IP addresses are supported */
++#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
++#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
++#define E1000_IP6AT_SIZE 1
++
++/* IPv6 Address Table Entry */
++struct e1000_ipv6_at_entry {
++ volatile uint8_t ipv6_addr[16];
++};
++
++/* Flexible Filter Length Table Entry */
++struct e1000_fflt_entry {
++ volatile uint32_t length; /* Flexible Filter Length (RW) */
++ volatile uint32_t reserved;
++};
++
++/* Flexible Filter Mask Table Entry */
++struct e1000_ffmt_entry {
++ volatile uint32_t mask; /* Flexible Filter Mask (RW) */
++ volatile uint32_t reserved;
++};
++
++/* Flexible Filter Value Table Entry */
++struct e1000_ffvt_entry {
++ volatile uint32_t value; /* Flexible Filter Value (RW) */
++ volatile uint32_t reserved;
++};
++
++/* Four Flexible Filters are supported */
++#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
++
++/* Each Flexible Filter is at most 128 (0x80) bytes in length */
++#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
++
++#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
++#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
++#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
++
++/* Register Set. (82543, 82544)
++ *
++ * Registers are defined to be 32 bits and should be accessed as 32 bit values.
++ * These registers are physically located on the NIC, but are mapped into the
++ * host memory address space.
++ *
++ * RW - register is both readable and writable
++ * RO - register is read only
++ * WO - register is write only
++ * R/clr - register is read only and is cleared when read
++ * A - register array
++ */
++#define E1000_CTRL 0x00000 /* Device Control - RW */
++#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
++#define E1000_STATUS 0x00008 /* Device Status - RO */
++#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
++#define E1000_EERD 0x00014 /* EEPROM Read - RW */
++#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
++#define E1000_FLA 0x0001C /* Flash Access - RW */
++#define E1000_MDIC 0x00020 /* MDI Control - RW */
++#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
++#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
++#define E1000_FCT 0x00030 /* Flow Control Type - RW */
++#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
++#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
++#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
++#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
++#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
++#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
++#define E1000_RCTL 0x00100 /* RX Control - RW */
++#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
++#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
++#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
++#define E1000_TCTL 0x00400 /* TX Control - RW */
++#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
++#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
++#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
++#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
++#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
++#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
++#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
++#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
++#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
++#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
++#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
++#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
++#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
++#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
++#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
++#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
++#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
++#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
++#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
++#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
++#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
++#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
++#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
++#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
++#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
++#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
++#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
++#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
++#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
++#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
++#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
++#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
++#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
++#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
++#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
++#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
++#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
++#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
++#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
++#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
++#define E1000_COLC 0x04028 /* Collision Count - R/clr */
++#define E1000_DC 0x04030 /* Defer Count - R/clr */
++#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
++#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
++#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
++#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
++#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
++#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
++#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
++#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
++#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
++#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
++#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
++#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
++#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
++#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
++#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
++#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
++#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
++#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
++#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
++#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
++#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
++#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
++#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
++#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
++#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
++#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
++#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
++#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
++#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
++#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
++#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
++#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
++#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
++#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
++#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
++#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
++#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
++#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
++#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
++#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
++#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
++#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
++#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
++#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
++#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
++#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
++#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
++#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
++#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
++#define E1000_RA 0x05400 /* Receive Address - RW Array */
++#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
++#define E1000_WUC 0x05800 /* Wakeup Control - RW */
++#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
++#define E1000_WUS 0x05810 /* Wakeup Status - RO */
++#define E1000_MANC 0x05820 /* Management Control - RW */
++#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
++#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
++#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
++#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
++#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
++#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
++#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
++#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
++
++/* Register Set (82542)
++ *
++ * Some of the 82542 registers are located at different offsets than they are
++ * in more current versions of the 8254x. Despite the difference in location,
++ * the registers function in the same manner.
++ */
++#define E1000_82542_CTRL E1000_CTRL
++#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
++#define E1000_82542_STATUS E1000_STATUS
++#define E1000_82542_EECD E1000_EECD
++#define E1000_82542_EERD E1000_EERD
++#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
++#define E1000_82542_FLA E1000_FLA
++#define E1000_82542_MDIC E1000_MDIC
++#define E1000_82542_FCAL E1000_FCAL
++#define E1000_82542_FCAH E1000_FCAH
++#define E1000_82542_FCT E1000_FCT
++#define E1000_82542_VET E1000_VET
++#define E1000_82542_RA 0x00040
++#define E1000_82542_ICR E1000_ICR
++#define E1000_82542_ITR E1000_ITR
++#define E1000_82542_ICS E1000_ICS
++#define E1000_82542_IMS E1000_IMS
++#define E1000_82542_IMC E1000_IMC
++#define E1000_82542_RCTL E1000_RCTL
++#define E1000_82542_RDTR 0x00108
++#define E1000_82542_RDBAL 0x00110
++#define E1000_82542_RDBAH 0x00114
++#define E1000_82542_RDLEN 0x00118
++#define E1000_82542_RDH 0x00120
++#define E1000_82542_RDT 0x00128
++#define E1000_82542_FCRTH 0x00160
++#define E1000_82542_FCRTL 0x00168
++#define E1000_82542_FCTTV E1000_FCTTV
++#define E1000_82542_TXCW E1000_TXCW
++#define E1000_82542_RXCW E1000_RXCW
++#define E1000_82542_MTA 0x00200
++#define E1000_82542_TCTL E1000_TCTL
++#define E1000_82542_TIPG E1000_TIPG
++#define E1000_82542_TDBAL 0x00420
++#define E1000_82542_TDBAH 0x00424
++#define E1000_82542_TDLEN 0x00428
++#define E1000_82542_TDH 0x00430
++#define E1000_82542_TDT 0x00438
++#define E1000_82542_TIDV 0x00440
++#define E1000_82542_TBT E1000_TBT
++#define E1000_82542_AIT E1000_AIT
++#define E1000_82542_VFTA 0x00600
++#define E1000_82542_LEDCTL E1000_LEDCTL
++#define E1000_82542_PBA E1000_PBA
++#define E1000_82542_RXDCTL E1000_RXDCTL
++#define E1000_82542_RADV E1000_RADV
++#define E1000_82542_RSRPD E1000_RSRPD
++#define E1000_82542_TXDMAC E1000_TXDMAC
++#define E1000_82542_TDFHS E1000_TDFHS
++#define E1000_82542_TDFTS E1000_TDFTS
++#define E1000_82542_TDFPC E1000_TDFPC
++#define E1000_82542_TXDCTL E1000_TXDCTL
++#define E1000_82542_TADV E1000_TADV
++#define E1000_82542_TSPMT E1000_TSPMT
++#define E1000_82542_CRCERRS E1000_CRCERRS
++#define E1000_82542_ALGNERRC E1000_ALGNERRC
++#define E1000_82542_SYMERRS E1000_SYMERRS
++#define E1000_82542_RXERRC E1000_RXERRC
++#define E1000_82542_MPC E1000_MPC
++#define E1000_82542_SCC E1000_SCC
++#define E1000_82542_ECOL E1000_ECOL
++#define E1000_82542_MCC E1000_MCC
++#define E1000_82542_LATECOL E1000_LATECOL
++#define E1000_82542_COLC E1000_COLC
++#define E1000_82542_DC E1000_DC
++#define E1000_82542_TNCRS E1000_TNCRS
++#define E1000_82542_SEC E1000_SEC
++#define E1000_82542_CEXTERR E1000_CEXTERR
++#define E1000_82542_RLEC E1000_RLEC
++#define E1000_82542_XONRXC E1000_XONRXC
++#define E1000_82542_XONTXC E1000_XONTXC
++#define E1000_82542_XOFFRXC E1000_XOFFRXC
++#define E1000_82542_XOFFTXC E1000_XOFFTXC
++#define E1000_82542_FCRUC E1000_FCRUC
++#define E1000_82542_PRC64 E1000_PRC64
++#define E1000_82542_PRC127 E1000_PRC127
++#define E1000_82542_PRC255 E1000_PRC255
++#define E1000_82542_PRC511 E1000_PRC511
++#define E1000_82542_PRC1023 E1000_PRC1023
++#define E1000_82542_PRC1522 E1000_PRC1522
++#define E1000_82542_GPRC E1000_GPRC
++#define E1000_82542_BPRC E1000_BPRC
++#define E1000_82542_MPRC E1000_MPRC
++#define E1000_82542_GPTC E1000_GPTC
++#define E1000_82542_GORCL E1000_GORCL
++#define E1000_82542_GORCH E1000_GORCH
++#define E1000_82542_GOTCL E1000_GOTCL
++#define E1000_82542_GOTCH E1000_GOTCH
++#define E1000_82542_RNBC E1000_RNBC
++#define E1000_82542_RUC E1000_RUC
++#define E1000_82542_RFC E1000_RFC
++#define E1000_82542_ROC E1000_ROC
++#define E1000_82542_RJC E1000_RJC
++#define E1000_82542_MGTPRC E1000_MGTPRC
++#define E1000_82542_MGTPDC E1000_MGTPDC
++#define E1000_82542_MGTPTC E1000_MGTPTC
++#define E1000_82542_TORL E1000_TORL
++#define E1000_82542_TORH E1000_TORH
++#define E1000_82542_TOTL E1000_TOTL
++#define E1000_82542_TOTH E1000_TOTH
++#define E1000_82542_TPR E1000_TPR
++#define E1000_82542_TPT E1000_TPT
++#define E1000_82542_PTC64 E1000_PTC64
++#define E1000_82542_PTC127 E1000_PTC127
++#define E1000_82542_PTC255 E1000_PTC255
++#define E1000_82542_PTC511 E1000_PTC511
++#define E1000_82542_PTC1023 E1000_PTC1023
++#define E1000_82542_PTC1522 E1000_PTC1522
++#define E1000_82542_MPTC E1000_MPTC
++#define E1000_82542_BPTC E1000_BPTC
++#define E1000_82542_TSCTC E1000_TSCTC
++#define E1000_82542_TSCTFC E1000_TSCTFC
++#define E1000_82542_RXCSUM E1000_RXCSUM
++#define E1000_82542_WUC E1000_WUC
++#define E1000_82542_WUFC E1000_WUFC
++#define E1000_82542_WUS E1000_WUS
++#define E1000_82542_MANC E1000_MANC
++#define E1000_82542_IPAV E1000_IPAV
++#define E1000_82542_IP4AT E1000_IP4AT
++#define E1000_82542_IP6AT E1000_IP6AT
++#define E1000_82542_WUPL E1000_WUPL
++#define E1000_82542_WUPM E1000_WUPM
++#define E1000_82542_FFLT E1000_FFLT
++#define E1000_82542_TDFH 0x08010
++#define E1000_82542_TDFT 0x08018
++#define E1000_82542_FFMT E1000_FFMT
++#define E1000_82542_FFVT E1000_FFVT
++
++/* Statistics counters collected by the MAC */
++struct e1000_hw_stats {
++ uint64_t crcerrs;
++ uint64_t algnerrc;
++ uint64_t symerrs;
++ uint64_t rxerrc;
++ uint64_t mpc;
++ uint64_t scc;
++ uint64_t ecol;
++ uint64_t mcc;
++ uint64_t latecol;
++ uint64_t colc;
++ uint64_t dc;
++ uint64_t tncrs;
++ uint64_t sec;
++ uint64_t cexterr;
++ uint64_t rlec;
++ uint64_t xonrxc;
++ uint64_t xontxc;
++ uint64_t xoffrxc;
++ uint64_t xofftxc;
++ uint64_t fcruc;
++ uint64_t prc64;
++ uint64_t prc127;
++ uint64_t prc255;
++ uint64_t prc511;
++ uint64_t prc1023;
++ uint64_t prc1522;
++ uint64_t gprc;
++ uint64_t bprc;
++ uint64_t mprc;
++ uint64_t gptc;
++ uint64_t gorcl;
++ uint64_t gorch;
++ uint64_t gotcl;
++ uint64_t gotch;
++ uint64_t rnbc;
++ uint64_t ruc;
++ uint64_t rfc;
++ uint64_t roc;
++ uint64_t rjc;
++ uint64_t mgprc;
++ uint64_t mgpdc;
++ uint64_t mgptc;
++ uint64_t torl;
++ uint64_t torh;
++ uint64_t totl;
++ uint64_t toth;
++ uint64_t tpr;
++ uint64_t tpt;
++ uint64_t ptc64;
++ uint64_t ptc127;
++ uint64_t ptc255;
++ uint64_t ptc511;
++ uint64_t ptc1023;
++ uint64_t ptc1522;
++ uint64_t mptc;
++ uint64_t bptc;
++ uint64_t tsctc;
++ uint64_t tsctfc;
++};
++
++/* Structure containing variables used by the shared code (e1000_hw.c) */
++struct e1000_hw {
++ struct pci_device *pdev;
++ uint8_t *hw_addr;
++ e1000_mac_type mac_type;
++ e1000_phy_type phy_type;
++#if 0
++ uint32_t phy_init_script;
++#endif
++ e1000_media_type media_type;
++ e1000_fc_type fc;
++#if 0
++ e1000_bus_speed bus_speed;
++ e1000_bus_width bus_width;
++ e1000_bus_type bus_type;
++#endif
++ struct e1000_eeprom_info eeprom;
++#if 0
++ e1000_ms_type master_slave;
++ e1000_ms_type original_master_slave;
++ e1000_ffe_config ffe_config_state;
++#endif
++ uint32_t io_base;
++ uint32_t phy_id;
++#ifdef LINUX_DRIVER
++ uint32_t phy_revision;
++#endif
++ uint32_t phy_addr;
++#if 0
++ uint32_t original_fc;
++#endif
++ uint32_t txcw;
++ uint32_t autoneg_failed;
++#if 0
++ uint32_t max_frame_size;
++ uint32_t min_frame_size;
++ uint32_t mc_filter_type;
++ uint32_t num_mc_addrs;
++ uint32_t collision_delta;
++ uint32_t tx_packet_delta;
++ uint32_t ledctl_default;
++ uint32_t ledctl_mode1;
++ uint32_t ledctl_mode2;
++ uint16_t phy_spd_default;
++#endif
++ uint16_t autoneg_advertised;
++ uint16_t pci_cmd_word;
++#if 0
++ uint16_t fc_high_water;
++ uint16_t fc_low_water;
++ uint16_t fc_pause_time;
++ uint16_t current_ifs_val;
++ uint16_t ifs_min_val;
++ uint16_t ifs_max_val;
++ uint16_t ifs_step_size;
++ uint16_t ifs_ratio;
++#endif
++ uint16_t device_id;
++ uint16_t vendor_id;
++#if 0
++ uint16_t subsystem_id;
++ uint16_t subsystem_vendor_id;
++#endif
++ uint8_t revision_id;
++#if 0
++ uint8_t autoneg;
++ uint8_t mdix;
++ uint8_t forced_speed_duplex;
++ uint8_t wait_autoneg_complete;
++ uint8_t dma_fairness;
++#endif
++ uint8_t mac_addr[NODE_ADDRESS_SIZE];
++#if 0
++ uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
++ boolean_t disable_polarity_correction;
++ boolean_t speed_downgraded;
++ e1000_dsp_config dsp_config_state;
++ boolean_t get_link_status;
++ boolean_t serdes_link_down;
++#endif
++ boolean_t tbi_compatibility_en;
++ boolean_t tbi_compatibility_on;
++#if 0
++ boolean_t phy_reset_disable;
++ boolean_t fc_send_xon;
++ boolean_t fc_strict_ieee;
++ boolean_t report_tx_early;
++ boolean_t adaptive_ifs;
++ boolean_t ifs_params_forced;
++ boolean_t in_ifs_mode;
++#endif
++};
++
++
++#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
++#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
++
++/* Register Bit Masks */
++/* Device Control */
++#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
++#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
++#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
++#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
++#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
++#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
++#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
++#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
++#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
++#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
++#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
++#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
++#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
++#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
++#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
++#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
++#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
++#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
++#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
++#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
++#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
++#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
++#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
++#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
++#define E1000_CTRL_RST 0x04000000 /* Global reset */
++#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
++#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
++#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
++#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
++#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
++
++/* Device Status */
++#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
++#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
++#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
++#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
++#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
++#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
++#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
++#define E1000_STATUS_SPEED_MASK 0x000000C0
++#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
++#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
++#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
++#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
++#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
++#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
++#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
++#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
++#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
++
++/* Constants used to intrepret the masked PCI-X bus speed. */
++#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
++#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
++#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
++
++/* EEPROM/Flash Control */
++#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
++#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
++#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
++#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
++#define E1000_EECD_FWE_MASK 0x00000030
++#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
++#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
++#define E1000_EECD_FWE_SHIFT 4
++#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
++#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
++#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
++#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
++#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
++ * (0-small, 1-large) */
++#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
++#ifndef E1000_EEPROM_GRANT_ATTEMPTS
++#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
++#endif
++
++/* EEPROM Read */
++#define E1000_EERD_START 0x00000001 /* Start Read */
++#define E1000_EERD_DONE 0x00000010 /* Read Done */
++#define E1000_EERD_ADDR_SHIFT 8
++#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
++#define E1000_EERD_DATA_SHIFT 16
++#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
++
++/* SPI EEPROM Status Register */
++#define EEPROM_STATUS_RDY_SPI 0x01
++#define EEPROM_STATUS_WEN_SPI 0x02
++#define EEPROM_STATUS_BP0_SPI 0x04
++#define EEPROM_STATUS_BP1_SPI 0x08
++#define EEPROM_STATUS_WPEN_SPI 0x80
++
++/* Extended Device Control */
++#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
++#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
++#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
++#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
++#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
++#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
++#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
++#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
++#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
++#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
++#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
++#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
++#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
++#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
++#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
++#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
++#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
++#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
++#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
++#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
++#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
++#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
++#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
++#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
++#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
++#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
++
++/* MDI Control */
++#define E1000_MDIC_DATA_MASK 0x0000FFFF
++#define E1000_MDIC_REG_MASK 0x001F0000
++#define E1000_MDIC_REG_SHIFT 16
++#define E1000_MDIC_PHY_MASK 0x03E00000
++#define E1000_MDIC_PHY_SHIFT 21
++#define E1000_MDIC_OP_WRITE 0x04000000
++#define E1000_MDIC_OP_READ 0x08000000
++#define E1000_MDIC_READY 0x10000000
++#define E1000_MDIC_INT_EN 0x20000000
++#define E1000_MDIC_ERROR 0x40000000
++
++/* LED Control */
++#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
++#define E1000_LEDCTL_LED0_MODE_SHIFT 0
++#define E1000_LEDCTL_LED0_IVRT 0x00000040
++#define E1000_LEDCTL_LED0_BLINK 0x00000080
++#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
++#define E1000_LEDCTL_LED1_MODE_SHIFT 8
++#define E1000_LEDCTL_LED1_IVRT 0x00004000
++#define E1000_LEDCTL_LED1_BLINK 0x00008000
++#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
++#define E1000_LEDCTL_LED2_MODE_SHIFT 16
++#define E1000_LEDCTL_LED2_IVRT 0x00400000
++#define E1000_LEDCTL_LED2_BLINK 0x00800000
++#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
++#define E1000_LEDCTL_LED3_MODE_SHIFT 24
++#define E1000_LEDCTL_LED3_IVRT 0x40000000
++#define E1000_LEDCTL_LED3_BLINK 0x80000000
++
++#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
++#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
++#define E1000_LEDCTL_MODE_LINK_UP 0x2
++#define E1000_LEDCTL_MODE_ACTIVITY 0x3
++#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
++#define E1000_LEDCTL_MODE_LINK_10 0x5
++#define E1000_LEDCTL_MODE_LINK_100 0x6
++#define E1000_LEDCTL_MODE_LINK_1000 0x7
++#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
++#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
++#define E1000_LEDCTL_MODE_COLLISION 0xA
++#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
++#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
++#define E1000_LEDCTL_MODE_PAUSED 0xD
++#define E1000_LEDCTL_MODE_LED_ON 0xE
++#define E1000_LEDCTL_MODE_LED_OFF 0xF
++
++/* Receive Address */
++#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
++
++/* Interrupt Cause Read */
++#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
++#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
++#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
++#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
++#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
++#define E1000_ICR_RXO 0x00000040 /* rx overrun */
++#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
++#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
++#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
++#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
++#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
++#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
++#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
++#define E1000_ICR_TXD_LOW 0x00008000
++#define E1000_ICR_SRPD 0x00010000
++
++/* Interrupt Cause Set */
++#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
++#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
++#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
++#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
++#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
++#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
++#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
++#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
++#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
++#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
++#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
++#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
++#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
++#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
++#define E1000_ICS_SRPD E1000_ICR_SRPD
++
++/* Interrupt Mask Set */
++#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
++#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
++#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
++#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
++#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
++#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
++#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
++#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
++#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
++#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
++#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
++#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
++#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
++#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
++#define E1000_IMS_SRPD E1000_ICR_SRPD
++
++/* Interrupt Mask Clear */
++#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
++#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
++#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
++#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
++#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
++#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
++#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
++#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
++#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
++#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
++#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
++#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
++#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
++#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
++#define E1000_IMC_SRPD E1000_ICR_SRPD
++
++/* Receive Control */
++#define E1000_RCTL_RST 0x00000001 /* Software reset */
++#define E1000_RCTL_EN 0x00000002 /* enable */
++#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
++#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
++#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
++#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
++#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
++#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
++#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
++#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
++#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
++#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
++#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
++#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
++#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
++#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
++#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
++#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
++#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
++#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
++/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
++#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
++#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
++#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
++#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
++/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
++#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
++#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
++#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
++#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
++#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
++#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
++#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
++#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
++#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
++
++/* Receive Descriptor */
++#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
++#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
++#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
++#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
++#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
++
++/* Flow Control */
++#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
++#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
++#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
++#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
++
++/* Receive Descriptor Control */
++#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
++#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
++#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
++#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
++
++/* Transmit Descriptor Control */
++#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
++#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
++#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
++#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
++#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
++#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
++
++/* Transmit Configuration Word */
++#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
++#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
++#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
++#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
++#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
++#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
++#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
++#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
++#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
++#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
++
++/* Receive Configuration Word */
++#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
++#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
++#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
++#define E1000_RXCW_CC 0x10000000 /* Receive config change */
++#define E1000_RXCW_C 0x20000000 /* Receive config */
++#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
++#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
++
++/* Transmit Control */
++#define E1000_TCTL_RST 0x00000001 /* software reset */
++#define E1000_TCTL_EN 0x00000002 /* enable tx */
++#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
++#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
++#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
++#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
++#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
++#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
++#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
++#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
++
++/* Receive Checksum Control */
++#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
++#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
++#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
++#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
++
++/* Definitions for power management and wakeup registers */
++/* Wake Up Control */
++#define E1000_WUC_APME 0x00000001 /* APM Enable */
++#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
++#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
++#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
++#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
++
++/* Wake Up Filter Control */
++#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
++#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
++#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
++#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
++#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
++#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
++#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
++#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
++#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
++#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
++#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
++#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
++#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
++#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
++#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
++
++/* Wake Up Status */
++#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
++#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
++#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
++#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
++#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
++#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
++#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
++#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
++#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
++#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
++#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
++#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
++#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
++
++/* Management Control */
++#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
++#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
++#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
++#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
++#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
++#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
++#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
++#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
++#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
++#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
++ * Filtering */
++#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
++#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
++#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
++#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
++#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
++#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
++#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
++#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
++#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
++
++#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
++#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
++
++/* Wake Up Packet Length */
++#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
++
++#define E1000_MDALIGN 4096
++
++/* EEPROM Commands - Microwire */
++#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
++#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
++#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
++#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
++#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
++
++/* EEPROM Commands - SPI */
++#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
++#define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */
++#define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */
++#define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */
++#define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */
++#define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */
++#define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */
++#define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */
++
++/* EEPROM Size definitions */
++#define EEPROM_SIZE_16KB 0x1800
++#define EEPROM_SIZE_8KB 0x1400
++#define EEPROM_SIZE_4KB 0x1000
++#define EEPROM_SIZE_2KB 0x0C00
++#define EEPROM_SIZE_1KB 0x0800
++#define EEPROM_SIZE_512B 0x0400
++#define EEPROM_SIZE_128B 0x0000
++#define EEPROM_SIZE_MASK 0x1C00
++
++/* EEPROM Word Offsets */
++#define EEPROM_COMPAT 0x0003
++#define EEPROM_ID_LED_SETTINGS 0x0004
++#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
++#define EEPROM_INIT_CONTROL1_REG 0x000A
++#define EEPROM_INIT_CONTROL2_REG 0x000F
++#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
++#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
++#define EEPROM_CFG 0x0012
++#define EEPROM_FLASH_VERSION 0x0032
++#define EEPROM_CHECKSUM_REG 0x003F
++
++/* Word definitions for ID LED Settings */
++#define ID_LED_RESERVED_0000 0x0000
++#define ID_LED_RESERVED_FFFF 0xFFFF
++#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
++ (ID_LED_OFF1_OFF2 << 8) | \
++ (ID_LED_DEF1_DEF2 << 4) | \
++ (ID_LED_DEF1_DEF2))
++#define ID_LED_DEF1_DEF2 0x1
++#define ID_LED_DEF1_ON2 0x2
++#define ID_LED_DEF1_OFF2 0x3
++#define ID_LED_ON1_DEF2 0x4
++#define ID_LED_ON1_ON2 0x5
++#define ID_LED_ON1_OFF2 0x6
++#define ID_LED_OFF1_DEF2 0x7
++#define ID_LED_OFF1_ON2 0x8
++#define ID_LED_OFF1_OFF2 0x9
++
++#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
++#define IGP_ACTIVITY_LED_ENABLE 0x0300
++#define IGP_LED3_MODE 0x07000000
++
++
++/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
++#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
++
++/* Mask bits for fields in Word 0x0a of the EEPROM */
++#define EEPROM_WORD0A_ILOS 0x0010
++#define EEPROM_WORD0A_SWDPIO 0x01E0
++#define EEPROM_WORD0A_LRST 0x0200
++#define EEPROM_WORD0A_FD 0x0400
++#define EEPROM_WORD0A_66MHZ 0x0800
++
++/* Mask bits for fields in Word 0x0f of the EEPROM */
++#define EEPROM_WORD0F_PAUSE_MASK 0x3000
++#define EEPROM_WORD0F_PAUSE 0x1000
++#define EEPROM_WORD0F_ASM_DIR 0x2000
++#define EEPROM_WORD0F_ANE 0x0800
++#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
++
++/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
++#define EEPROM_SUM 0xBABA
++
++/* EEPROM Map defines (WORD OFFSETS)*/
++#define EEPROM_NODE_ADDRESS_BYTE_0 0
++#define EEPROM_PBA_BYTE_1 8
++
++#define EEPROM_RESERVED_WORD 0xFFFF
++
++/* EEPROM Map Sizes (Byte Counts) */
++#define PBA_SIZE 4
++
++/* Collision related configuration parameters */
++#define E1000_COLLISION_THRESHOLD 16
++#define E1000_CT_SHIFT 4
++#define E1000_COLLISION_DISTANCE 64
++#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
++#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
++#define E1000_COLD_SHIFT 12
++
++/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
++#define REQ_TX_DESCRIPTOR_MULTIPLE 8
++#define REQ_RX_DESCRIPTOR_MULTIPLE 8
++
++/* Default values for the transmit IPG register */
++#define DEFAULT_82542_TIPG_IPGT 10
++#define DEFAULT_82543_TIPG_IPGT_FIBER 9
++#define DEFAULT_82543_TIPG_IPGT_COPPER 8
++
++#define E1000_TIPG_IPGT_MASK 0x000003FF
++#define E1000_TIPG_IPGR1_MASK 0x000FFC00
++#define E1000_TIPG_IPGR2_MASK 0x3FF00000
++
++#define DEFAULT_82542_TIPG_IPGR1 2
++#define DEFAULT_82543_TIPG_IPGR1 8
++#define E1000_TIPG_IPGR1_SHIFT 10
++
++#define DEFAULT_82542_TIPG_IPGR2 10
++#define DEFAULT_82543_TIPG_IPGR2 6
++#define E1000_TIPG_IPGR2_SHIFT 20
++
++#define E1000_TXDMAC_DPP 0x00000001
++
++/* Adaptive IFS defines */
++#define TX_THRESHOLD_START 8
++#define TX_THRESHOLD_INCREMENT 10
++#define TX_THRESHOLD_DECREMENT 1
++#define TX_THRESHOLD_STOP 190
++#define TX_THRESHOLD_DISABLE 0
++#define TX_THRESHOLD_TIMER_MS 10000
++#define MIN_NUM_XMITS 1000
++#define IFS_MAX 80
++#define IFS_STEP 10
++#define IFS_MIN 40
++#define IFS_RATIO 4
++
++/* PBA constants */
++#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
++#define E1000_PBA_22K 0x0016
++#define E1000_PBA_24K 0x0018
++#define E1000_PBA_30K 0x001E
++#define E1000_PBA_40K 0x0028
++#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
++
++/* Flow Control Constants */
++#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
++#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
++#define FLOW_CONTROL_TYPE 0x8808
++
++/* The historical defaults for the flow control values are given below. */
++#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
++#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
++#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
++
++/* PCIX Config space */
++#define PCIX_COMMAND_REGISTER 0xE6
++#define PCIX_STATUS_REGISTER_LO 0xE8
++#define PCIX_STATUS_REGISTER_HI 0xEA
++
++#define PCIX_COMMAND_MMRBC_MASK 0x000C
++#define PCIX_COMMAND_MMRBC_SHIFT 0x2
++#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
++#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
++#define PCIX_STATUS_HI_MMRBC_4K 0x3
++#define PCIX_STATUS_HI_MMRBC_2K 0x2
++
++
++/* Number of bits required to shift right the "pause" bits from the
++ * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
++ */
++#define PAUSE_SHIFT 5
++
++/* Number of bits required to shift left the "SWDPIO" bits from the
++ * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
++ */
++#define SWDPIO_SHIFT 17
++
++/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
++ * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
++ */
++#define SWDPIO__EXT_SHIFT 4
++
++/* Number of bits required to shift left the "ILOS" bit from the EEPROM
++ * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
++ */
++#define ILOS_SHIFT 3
++
++
++#define RECEIVE_BUFFER_ALIGN_SIZE (256)
++
++/* Number of milliseconds we wait for auto-negotiation to complete */
++#define LINK_UP_TIMEOUT 500
++
++#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
++
++/* The carrier extension symbol, as received by the NIC. */
++#define CARRIER_EXTENSION 0x0F
++
++/* TBI_ACCEPT macro definition:
++ *
++ * This macro requires:
++ * adapter = a pointer to struct e1000_hw
++ * status = the 8 bit status field of the RX descriptor with EOP set
++ * error = the 8 bit error field of the RX descriptor with EOP set
++ * length = the sum of all the length fields of the RX descriptors that
++ * make up the current frame
++ * last_byte = the last byte of the frame DMAed by the hardware
++ * max_frame_length = the maximum frame length we want to accept.
++ * min_frame_length = the minimum frame length we want to accept.
++ *
++ * This macro is a conditional that should be used in the interrupt
++ * handler's Rx processing routine when RxErrors have been detected.
++ *
++ * Typical use:
++ * ...
++ * if (TBI_ACCEPT) {
++ * accept_frame = TRUE;
++ * e1000_tbi_adjust_stats(adapter, MacAddress);
++ * frame_length--;
++ * } else {
++ * accept_frame = FALSE;
++ * }
++ * ...
++ */
++
++#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
++ ((adapter)->tbi_compatibility_on && \
++ (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
++ ((last_byte) == CARRIER_EXTENSION) && \
++ (((status) & E1000_RXD_STAT_VP) ? \
++ (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
++ ((length) <= ((adapter)->max_frame_size + 1))) : \
++ (((length) > (adapter)->min_frame_size) && \
++ ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
++
++
++/* Structures, enums, and macros for the PHY */
++
++/* Bit definitions for the Management Data IO (MDIO) and Management Data
++ * Clock (MDC) pins in the Device Control Register.
++ */
++#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
++#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
++#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
++#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
++#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
++#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
++#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
++#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
++
++/* PHY 1000 MII Register/Bit Definitions */
++/* PHY Registers defined by IEEE */
++#define PHY_CTRL 0x00 /* Control Register */
++#define PHY_STATUS 0x01 /* Status Regiser */
++#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
++#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
++#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
++#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
++#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
++#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
++#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
++#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
++#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
++#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
++
++/* M88E1000 Specific Registers */
++#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
++#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
++#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
++#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
++#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
++#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
++
++#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
++#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
++#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
++#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
++#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
++
++#define IGP01E1000_IEEE_REGS_PAGE 0x0000
++#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
++#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
++
++/* IGP01E1000 Specific Registers */
++#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
++#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
++#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
++#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
++#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
++#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
++#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
++
++/* IGP01E1000 AGC Registers - stores the cable length values*/
++#define IGP01E1000_PHY_AGC_A 0x1172
++#define IGP01E1000_PHY_AGC_B 0x1272
++#define IGP01E1000_PHY_AGC_C 0x1472
++#define IGP01E1000_PHY_AGC_D 0x1872
++
++/* IGP01E1000 DSP Reset Register */
++#define IGP01E1000_PHY_DSP_RESET 0x1F33
++#define IGP01E1000_PHY_DSP_SET 0x1F71
++#define IGP01E1000_PHY_DSP_FFE 0x1F35
++
++#define IGP01E1000_PHY_CHANNEL_NUM 4
++#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
++#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
++#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
++#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
++
++#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
++#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
++
++#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
++#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
++#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
++#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
++
++#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
++/* IGP01E1000 PCS Initialization register - stores the polarity status when
++ * speed = 1000 Mbps. */
++#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
++#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
++
++#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
++
++#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
++#define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/
++/* PHY Control Register */
++#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
++#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
++#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
++#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
++#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
++#define MII_CR_POWER_DOWN 0x0800 /* Power down */
++#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
++#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
++#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
++#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
++
++/* PHY Status Register */
++#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
++#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
++#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
++#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
++#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
++#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
++#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
++#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
++#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
++#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
++#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
++#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
++#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
++#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
++#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
++
++/* Autoneg Advertisement Register */
++#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
++#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
++#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
++#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
++#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
++#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
++#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
++#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
++#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
++#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
++
++/* Link Partner Ability Register (Base Page) */
++#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
++#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
++#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
++#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
++#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
++#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
++#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
++#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
++#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
++#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
++#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
++
++/* Autoneg Expansion Register */
++#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
++#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
++#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
++#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
++#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
++
++/* Next Page TX Register */
++#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
++#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
++ * of different NP
++ */
++#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
++ * 0 = cannot comply with msg
++ */
++#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
++#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
++ * 0 = sending last NP
++ */
++
++/* Link Partner Next Page Register */
++#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
++#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
++ * of different NP
++ */
++#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
++ * 0 = cannot comply with msg
++ */
++#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
++#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
++#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
++ * 0 = sending last NP
++ */
++
++/* 1000BASE-T Control Register */
++#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
++#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
++#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
++#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
++ /* 0=DTE device */
++#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
++ /* 0=Configure PHY as Slave */
++#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
++ /* 0=Automatic Master/Slave config */
++#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
++#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
++#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
++#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
++#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
++
++/* 1000BASE-T Status Register */
++#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
++#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
++#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
++#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
++#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
++#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
++#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
++#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
++#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
++#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
++#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
++#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
++#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
++
++/* Extended Status Register */
++#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
++#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
++#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
++#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
++
++#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
++#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
++
++#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
++ /* (0=enable, 1=disable) */
++
++/* M88E1000 PHY Specific Control Register */
++#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
++#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
++#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
++#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
++ * 0=CLK125 toggling
++ */
++#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
++ /* Manual MDI configuration */
++#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
++#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
++ * 100BASE-TX/10BASE-T:
++ * MDI Mode
++ */
++#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
++ * all speeds.
++ */
++#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
++ /* 1=Enable Extended 10BASE-T distance
++ * (Lower 10BASE-T RX Threshold)
++ * 0=Normal 10BASE-T RX Threshold */
++#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
++ /* 1=5-Bit interface in 100BASE-TX
++ * 0=MII interface in 100BASE-TX */
++#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
++#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
++#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
++
++#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
++#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
++#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
++
++/* M88E1000 PHY Specific Status Register */
++#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
++#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
++#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
++#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
++#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
++ * 3=110-140M;4=>140M */
++#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
++#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
++#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
++#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
++#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
++#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
++#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
++#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
++
++#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
++#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
++#define M88E1000_PSSR_MDIX_SHIFT 6
++#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
++
++/* M88E1000 Extended PHY Specific Control Register */
++#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
++#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
++ * Will assert lost lock and bring
++ * link down if idle not seen
++ * within 1ms in 1000BASE-T
++ */
++/* Number of times we will attempt to autonegotiate before downshifting if we
++ * are the master */
++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
++/* Number of times we will attempt to autonegotiate before downshifting if we
++ * are the slave */
++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
++#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
++#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
++#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
++
++/* IGP01E1000 Specific Port Config Register - R/W */
++#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
++#define IGP01E1000_PSCFR_PRE_EN 0x0020
++#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
++#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
++#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
++#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
++
++/* IGP01E1000 Specific Port Status Register - R/O */
++#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
++#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
++#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
++#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
++#define IGP01E1000_PSSR_LINK_UP 0x0400
++#define IGP01E1000_PSSR_MDIX 0x0800
++#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
++#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
++#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
++#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
++#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
++#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
++
++/* IGP01E1000 Specific Port Control Register - R/W */
++#define IGP01E1000_PSCR_TP_LOOPBACK 0x0001
++#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
++#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
++#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
++#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
++#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
++
++/* IGP01E1000 Specific Port Link Health Register */
++#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
++#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
++#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
++#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
++#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
++#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
++#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0010
++#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0008
++#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0004
++#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0002
++#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0001
++#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0000
++
++/* IGP01E1000 Channel Quality Register */
++#define IGP01E1000_MSE_CHANNEL_D 0x000F
++#define IGP01E1000_MSE_CHANNEL_C 0x00F0
++#define IGP01E1000_MSE_CHANNEL_B 0x0F00
++#define IGP01E1000_MSE_CHANNEL_A 0xF000
++
++/* IGP01E1000 DSP reset macros */
++#define DSP_RESET_ENABLE 0x0
++#define DSP_RESET_DISABLE 0x2
++#define E1000_MAX_DSP_RESETS 10
++
++/* IGP01E1000 AGC Registers */
++
++#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
++
++/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
++#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
++
++/* The precision of the length is +/- 10 meters */
++#define IGP01E1000_AGC_RANGE 10
++
++/* IGP01E1000 PCS Initialization register */
++/* bits 3:6 in the PCS registers stores the channels polarity */
++#define IGP01E1000_PHY_POLARITY_MASK 0x0078
++
++/* IGP01E1000 GMII FIFO Register */
++#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
++ * on Link-Up */
++#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
++
++/* IGP01E1000 Analog Register */
++#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
++#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
++#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
++#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
++
++#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
++#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
++#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
++#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
++#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
++
++#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
++#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
++#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
++#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
++
++/* Bit definitions for valid PHY IDs. */
++#define M88E1000_E_PHY_ID 0x01410C50
++#define M88E1000_I_PHY_ID 0x01410C30
++#define M88E1011_I_PHY_ID 0x01410C20
++#define IGP01E1000_I_PHY_ID 0x02A80380
++#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
++#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
++#define M88E1011_I_REV_4 0x04
++
++/* Miscellaneous PHY bit definitions. */
++#define PHY_PREAMBLE 0xFFFFFFFF
++#define PHY_SOF 0x01
++#define PHY_OP_READ 0x02
++#define PHY_OP_WRITE 0x01
++#define PHY_TURNAROUND 0x02
++#define PHY_PREAMBLE_SIZE 32
++#define MII_CR_SPEED_1000 0x0040
++#define MII_CR_SPEED_100 0x2000
++#define MII_CR_SPEED_10 0x0000
++#define E1000_PHY_ADDRESS 0x01
++#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
++#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
++#define PHY_REVISION_MASK 0xFFFFFFF0
++#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
++#define REG4_SPEED_MASK 0x01E0
++#define REG9_SPEED_MASK 0x0300
++#define ADVERTISE_10_HALF 0x0001
++#define ADVERTISE_10_FULL 0x0002
++#define ADVERTISE_100_HALF 0x0004
++#define ADVERTISE_100_FULL 0x0008
++#define ADVERTISE_1000_HALF 0x0010
++#define ADVERTISE_1000_FULL 0x0020
++#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
++#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
++#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
++
++#endif /* _E1000_HW_H_ */
+diff -Naur grub-0.97.orig/netboot/eepro.c grub-0.97/netboot/eepro.c
+--- grub-0.97.orig/netboot/eepro.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/eepro.c 1970-01-01 00:00:00.000000000 +0000
+@@ -1,586 +0,0 @@
+-/**************************************************************************
+-Etherboot - BOOTP/TFTP Bootstrap Program
+-Intel EEPRO/10 NIC driver for Etherboot
+-Adapted from Linux eepro.c from kernel 2.2.17
+-
+-This board accepts a 32 pin EEPROM (29C256), however a test with a
+-27C010 shows that this EPROM also works in the socket, but it's not clear
+-how repeatably. The two top address pins appear to be held low, thus
+-the bottom 32kB of the 27C010 is visible in the CPU's address space.
+-To be sure you could put 4 copies of the code in the 27C010, then
+-it doesn't matter whether the extra lines are held low or high, just
+-hopefully not floating as CMOS chips don't like floating inputs.
+-
+-Be careful with seating the EPROM as the socket on my board actually
+-has 34 pins, the top row of 2 are not used.
+-***************************************************************************/
+-
+-/*
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2, or (at
+- * your option) any later version.
+- */
+-
+-/* to get some global routines like printf */
+-#include "etherboot.h"
+-/* to get the interface to the body of the program */
+-#include "nic.h"
+-/* to get our own prototype */
+-#include "cards.h"
+-/* we use timer2 for microsecond waits */
+-#include "timer.h"
+-
+-#undef DEBUG /* only after include files */
+-
+-/* Different 82595 chips */
+-#define LAN595 0
+-#define LAN595TX 1
+-#define LAN595FX 2
+-#define LAN595FX_10ISA 3
+-
+-#define SLOW_DOWN inb(0x80);
+-
+-/* The station (ethernet) address prefix, used for IDing the board. */
+-#define SA_ADDR0 0x00 /* Etherexpress Pro/10 */
+-#define SA_ADDR1 0xaa
+-#define SA_ADDR2 0x00
+-
+-#define GetBit(x,y) ((x & (1<<y))>>y)
+-
+-/* EEPROM Word 0: */
+-#define ee_PnP 0 /* Plug 'n Play enable bit */
+-#define ee_Word1 1 /* Word 1? */
+-#define ee_BusWidth 2 /* 8/16 bit */
+-#define ee_FlashAddr 3 /* Flash Address */
+-#define ee_FlashMask 0x7 /* Mask */
+-#define ee_AutoIO 6 /* */
+-#define ee_reserved0 7 /* =0! */
+-#define ee_Flash 8 /* Flash there? */
+-#define ee_AutoNeg 9 /* Auto Negotiation enabled? */
+-#define ee_IO0 10 /* IO Address LSB */
+-#define ee_IO0Mask 0x /*...*/
+-#define ee_IO1 15 /* IO MSB */
+-
+-/* EEPROM Word 1: */
+-#define ee_IntSel 0 /* Interrupt */
+-#define ee_IntMask 0x7
+-#define ee_LI 3 /* Link Integrity 0= enabled */
+-#define ee_PC 4 /* Polarity Correction 0= enabled */
+-#define ee_TPE_AUI 5 /* PortSelection 1=TPE */
+-#define ee_Jabber 6 /* Jabber prevention 0= enabled */
+-#define ee_AutoPort 7 /* Auto Port Selection 1= Disabled */
+-#define ee_SMOUT 8 /* SMout Pin Control 0= Input */
+-#define ee_PROM 9 /* Flash EPROM / PROM 0=Flash */
+-#define ee_reserved1 10 /* .. 12 =0! */
+-#define ee_AltReady 13 /* Alternate Ready, 0=normal */
+-#define ee_reserved2 14 /* =0! */
+-#define ee_Duplex 15
+-
+-/* Word2,3,4: */
+-#define ee_IA5 0 /*bit start for individual Addr Byte 5 */
+-#define ee_IA4 8 /*bit start for individual Addr Byte 5 */
+-#define ee_IA3 0 /*bit start for individual Addr Byte 5 */
+-#define ee_IA2 8 /*bit start for individual Addr Byte 5 */
+-#define ee_IA1 0 /*bit start for individual Addr Byte 5 */
+-#define ee_IA0 8 /*bit start for individual Addr Byte 5 */
+-
+-/* Word 5: */
+-#define ee_BNC_TPE 0 /* 0=TPE */
+-#define ee_BootType 1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */
+-#define ee_BootTypeMask 0x3
+-#define ee_NumConn 3 /* Number of Connections 0= One or Two */
+-#define ee_FlashSock 4 /* Presence of Flash Socket 0= Present */
+-#define ee_PortTPE 5
+-#define ee_PortBNC 6
+-#define ee_PortAUI 7
+-#define ee_PowerMgt 10 /* 0= disabled */
+-#define ee_CP 13 /* Concurrent Processing */
+-#define ee_CPMask 0x7
+-
+-/* Word 6: */
+-#define ee_Stepping 0 /* Stepping info */
+-#define ee_StepMask 0x0F
+-#define ee_BoardID 4 /* Manucaturer Board ID, reserved */
+-#define ee_BoardMask 0x0FFF
+-
+-/* Word 7: */
+-#define ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */
+-#define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */
+-
+-/*..*/
+-#define ee_SIZE 0x40 /* total EEprom Size */
+-#define ee_Checksum 0xBABA /* initial and final value for adding checksum */
+-
+-
+-/* Card identification via EEprom: */
+-#define ee_addr_vendor 0x10 /* Word offset for EISA Vendor ID */
+-#define ee_addr_id 0x11 /* Word offset for Card ID */
+-#define ee_addr_SN 0x12 /* Serial Number */
+-#define ee_addr_CRC_8 0x14 /* CRC over last thee Bytes */
+-
+-
+-#define ee_vendor_intel0 0x25 /* Vendor ID Intel */
+-#define ee_vendor_intel1 0xD4
+-#define ee_id_eepro10p0 0x10 /* ID for eepro/10+ */
+-#define ee_id_eepro10p1 0x31
+-
+-/* now this section could be used by both boards: the oldies and the ee10:
+- * ee10 uses tx buffer before of rx buffer and the oldies the inverse.
+- * (aris)
+- */
+-#define RAM_SIZE 0x8000
+-
+-#define RCV_HEADER 8
+-#define RCV_DEFAULT_RAM 0x6000
+-#define RCV_RAM rcv_ram
+-
+-static unsigned rcv_ram = RCV_DEFAULT_RAM;
+-
+-#define XMT_HEADER 8
+-#define XMT_RAM (RAM_SIZE - RCV_RAM)
+-
+-#define XMT_START ((rcv_start + RCV_RAM) % RAM_SIZE)
+-
+-#define RCV_LOWER_LIMIT (rcv_start >> 8)
+-#define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8)
+-#define XMT_LOWER_LIMIT (XMT_START >> 8)
+-#define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8)
+-
+-#define RCV_START_PRO 0x00
+-#define RCV_START_10 XMT_RAM
+- /* by default the old driver */
+-static unsigned rcv_start = RCV_START_PRO;
+-
+-#define RCV_DONE 0x0008
+-#define RX_OK 0x2000
+-#define RX_ERROR 0x0d81
+-
+-#define TX_DONE_BIT 0x0080
+-#define CHAIN_BIT 0x8000
+-#define XMT_STATUS 0x02
+-#define XMT_CHAIN 0x04
+-#define XMT_COUNT 0x06
+-
+-#define BANK0_SELECT 0x00
+-#define BANK1_SELECT 0x40
+-#define BANK2_SELECT 0x80
+-
+-/* Bank 0 registers */
+-#define COMMAND_REG 0x00 /* Register 0 */
+-#define MC_SETUP 0x03
+-#define XMT_CMD 0x04
+-#define DIAGNOSE_CMD 0x07
+-#define RCV_ENABLE_CMD 0x08
+-#define RCV_DISABLE_CMD 0x0a
+-#define STOP_RCV_CMD 0x0b
+-#define RESET_CMD 0x0e
+-#define POWER_DOWN_CMD 0x18
+-#define RESUME_XMT_CMD 0x1c
+-#define SEL_RESET_CMD 0x1e
+-#define STATUS_REG 0x01 /* Register 1 */
+-#define RX_INT 0x02
+-#define TX_INT 0x04
+-#define EXEC_STATUS 0x30
+-#define ID_REG 0x02 /* Register 2 */
+-#define R_ROBIN_BITS 0xc0 /* round robin counter */
+-#define ID_REG_MASK 0x2c
+-#define ID_REG_SIG 0x24
+-#define AUTO_ENABLE 0x10
+-#define INT_MASK_REG 0x03 /* Register 3 */
+-#define RX_STOP_MASK 0x01
+-#define RX_MASK 0x02
+-#define TX_MASK 0x04
+-#define EXEC_MASK 0x08
+-#define ALL_MASK 0x0f
+-#define IO_32_BIT 0x10
+-#define RCV_BAR 0x04 /* The following are word (16-bit) registers */
+-#define RCV_STOP 0x06
+-
+-#define XMT_BAR_PRO 0x0a
+-#define XMT_BAR_10 0x0b
+-static unsigned xmt_bar = XMT_BAR_PRO;
+-
+-#define HOST_ADDRESS_REG 0x0c
+-#define IO_PORT 0x0e
+-#define IO_PORT_32_BIT 0x0c
+-
+-/* Bank 1 registers */
+-#define REG1 0x01
+-#define WORD_WIDTH 0x02
+-#define INT_ENABLE 0x80
+-#define INT_NO_REG 0x02
+-#define RCV_LOWER_LIMIT_REG 0x08
+-#define RCV_UPPER_LIMIT_REG 0x09
+-
+-#define XMT_LOWER_LIMIT_REG_PRO 0x0a
+-#define XMT_UPPER_LIMIT_REG_PRO 0x0b
+-#define XMT_LOWER_LIMIT_REG_10 0x0b
+-#define XMT_UPPER_LIMIT_REG_10 0x0a
+-static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO;
+-static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO;
+-
+-/* Bank 2 registers */
+-#define XMT_Chain_Int 0x20 /* Interrupt at the end of the transmit chain */
+-#define XMT_Chain_ErrStop 0x40 /* Interrupt at the end of the chain even if there are errors */
+-#define RCV_Discard_BadFrame 0x80 /* Throw bad frames away, and continue to receive others */
+-#define REG2 0x02
+-#define PRMSC_Mode 0x01
+-#define Multi_IA 0x20
+-#define REG3 0x03
+-#define TPE_BIT 0x04
+-#define BNC_BIT 0x20
+-#define REG13 0x0d
+-#define FDX 0x00
+-#define A_N_ENABLE 0x02
+-
+-#define I_ADD_REG0 0x04
+-#define I_ADD_REG1 0x05
+-#define I_ADD_REG2 0x06
+-#define I_ADD_REG3 0x07
+-#define I_ADD_REG4 0x08
+-#define I_ADD_REG5 0x09
+-
+-#define EEPROM_REG_PRO 0x0a
+-#define EEPROM_REG_10 0x0b
+-static unsigned eeprom_reg = EEPROM_REG_PRO;
+-
+-#define EESK 0x01
+-#define EECS 0x02
+-#define EEDI 0x04
+-#define EEDO 0x08
+-
+-/* The horrible routine to read a word from the serial EEPROM. */
+-/* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */
+-
+-/* The delay between EEPROM clock transitions. */
+-#define eeprom_delay() { udelay(40); }
+-#define EE_READ_CMD (6 << 6)
+-
+-/* do a full reset */
+-#define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(40);
+-
+-/* do a nice reset */
+-#define eepro_sel_reset(ioaddr) { \
+- outb(SEL_RESET_CMD, ioaddr); \
+- SLOW_DOWN; \
+- SLOW_DOWN; \
+- }
+-
+-/* clear all interrupts */
+-#define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
+-
+-/* enable rx */
+-#define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr)
+-
+-/* disable rx */
+-#define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr)
+-
+-/* switch bank */
+-#define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
+-#define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
+-#define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
+-
+-static unsigned int rx_start, tx_start;
+-static int tx_last;
+-static unsigned tx_end;
+-static int eepro = 0;
+-static unsigned short ioaddr = 0;
+-static unsigned int mem_start, mem_end = RCV_DEFAULT_RAM / 1024;
+-
+-#define udelay(n) waiton_timer2(((n)*TICKS_PER_MS)/1000)
+-
+-/**************************************************************************
+-RESET - Reset adapter
+-***************************************************************************/
+-static void eepro_reset(struct nic *nic)
+-{
+- int temp_reg, i;
+-
+- /* put the card in its initial state */
+- eepro_sw2bank2(ioaddr); /* be careful, bank2 now */
+- temp_reg = inb(ioaddr + eeprom_reg);
+-#ifdef DEBUG
+- printf("Stepping %d\n", temp_reg >> 5);
+-#endif
+- if (temp_reg & 0x10) /* check the TurnOff Enable bit */
+- outb(temp_reg & 0xEF, ioaddr + eeprom_reg);
+- for (i = 0; i < ETH_ALEN; i++) /* fill the MAC address */
+- outb(nic->node_addr[i], ioaddr + I_ADD_REG0 + i);
+- temp_reg = inb(ioaddr + REG1);
+- /* setup Transmit Chaining and discard bad RCV frames */
+- outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop
+- | RCV_Discard_BadFrame, ioaddr + REG1);
+- temp_reg = inb(ioaddr + REG2); /* match broadcast */
+- outb(temp_reg | 0x14, ioaddr + REG2);
+- temp_reg = inb(ioaddr + REG3);
+- outb(temp_reg & 0x3F, ioaddr + REG3); /* clear test mode */
+- /* set the receiving mode */
+- eepro_sw2bank1(ioaddr); /* be careful, bank1 now */
+- /* initialise the RCV and XMT upper and lower limits */
+- outb(RCV_LOWER_LIMIT, ioaddr + RCV_LOWER_LIMIT_REG);
+- outb(RCV_UPPER_LIMIT, ioaddr + RCV_UPPER_LIMIT_REG);
+- outb(XMT_LOWER_LIMIT, ioaddr + xmt_lower_limit_reg);
+- outb(XMT_UPPER_LIMIT, ioaddr + xmt_upper_limit_reg);
+- eepro_sw2bank0(ioaddr); /* Switch back to bank 0 */
+- eepro_clear_int(ioaddr);
+- /* Initialise RCV */
+- outw(rx_start = (RCV_LOWER_LIMIT << 8), ioaddr + RCV_BAR);
+- outw(((RCV_UPPER_LIMIT << 8) | 0xFE), ioaddr + RCV_STOP);
+- /* Intialise XMT */
+- outw((XMT_LOWER_LIMIT << 8), ioaddr + xmt_bar);
+- eepro_sel_reset(ioaddr);
+- tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
+- tx_last = 0;
+- eepro_en_rx(ioaddr);
+-}
+-
+-/**************************************************************************
+-POLL - Wait for a frame
+-***************************************************************************/
+-static int eepro_poll(struct nic *nic)
+-{
+- int i;
+- unsigned int rcv_car = rx_start;
+- unsigned int rcv_event, rcv_status, rcv_next_frame, rcv_size;
+-
+- /* return true if there's an ethernet packet ready to read */
+- /* nic->packet should contain data on return */
+- /* nic->packetlen should contain length of data */
+-#if 0
+- if ((inb(ioaddr + STATUS_REG) & 0x40) == 0)
+- return (0);
+- outb(0x40, ioaddr + STATUS_REG);
+-#endif
+- outw(rcv_car, ioaddr + HOST_ADDRESS_REG);
+- rcv_event = inw(ioaddr + IO_PORT);
+- if (rcv_event != RCV_DONE)
+- return (0);
+- rcv_status = inw(ioaddr + IO_PORT);
+- rcv_next_frame = inw(ioaddr + IO_PORT);
+- rcv_size = inw(ioaddr + IO_PORT);
+-#if 0
+- printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size,
+- inb(ioaddr + STATUS_REG));
+-#endif
+- if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) {
+- printf("Receive error %hX\n", rcv_status);
+- return (0);
+- }
+- rcv_size &= 0x3FFF;
+- insw(ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
+-#if 0
+- for (i = 0; i < 48; i++) {
+- printf("%hhX", nic->packet[i]);
+- putchar(i % 16 == 15 ? '\n' : ' ');
+- }
+-#endif
+- nic->packetlen = rcv_size;
+- rcv_car = rx_start + RCV_HEADER + rcv_size;
+- rx_start = rcv_next_frame;
+- if (rcv_car == 0)
+- rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff);
+- outw(rcv_car - 1, ioaddr + RCV_STOP);
+- return (1);
+-}
+-
+-/**************************************************************************
+-TRANSMIT - Transmit a frame
+-***************************************************************************/
+-static void eepro_transmit(
+- struct nic *nic,
+- const char *d, /* Destination */
+- unsigned int t, /* Type */
+- unsigned int s, /* size */
+- const char *p) /* Packet */
+-{
+- unsigned int status, tx_available, last, end, length;
+- unsigned short type;
+- int boguscount = 20;
+-
+- length = s + ETH_HLEN;
+- if (tx_end > tx_start)
+- tx_available = XMT_RAM - (tx_end - tx_start);
+- else if (tx_end < tx_start)
+- tx_available = tx_start - tx_end;
+- else
+- tx_available = XMT_RAM;
+- last = tx_end;
+- end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
+- if (end >= (XMT_UPPER_LIMIT << 8)) {
+- last = (XMT_LOWER_LIMIT << 8);
+- end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
+- }
+- outw(last, ioaddr + HOST_ADDRESS_REG);
+- outw(XMT_CMD, ioaddr + IO_PORT);
+- outw(0, ioaddr + IO_PORT);
+- outw(end, ioaddr + IO_PORT);
+- outw(length, ioaddr + IO_PORT);
+- outsw(ioaddr + IO_PORT, d, ETH_ALEN / 2);
+- outsw(ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2);
+- type = htons(t);
+- outsw(ioaddr + IO_PORT, &type, sizeof(type) / 2);
+- outsw(ioaddr + IO_PORT, p, (s + 3) >> 1);
+- /* A dummy read to flush the DRAM write pipeline */
+- status = inw(ioaddr + IO_PORT);
+- outw(last, ioaddr + xmt_bar);
+- outb(XMT_CMD, ioaddr);
+- tx_start = last;
+- tx_last = last;
+- tx_end = end;
+-#if 0
+- printf("%d %d\n", tx_start, tx_end);
+-#endif
+- while (boguscount > 0) {
+- if (((status = inw(ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
+- udelay(40);
+- boguscount--;
+- continue;
+- }
+-#if DEBUG
+- if ((status & 0x2000) == 0)
+- printf("Transmit status %hX\n", status);
+-#endif
+- }
+-}
+-
+-/**************************************************************************
+-DISABLE - Turn off ethernet interface
+-***************************************************************************/
+-static void eepro_disable(struct nic *nic)
+-{
+- eepro_sw2bank0(ioaddr); /* Switch to bank 0 */
+- /* Flush the Tx and disable Rx */
+- outb(STOP_RCV_CMD, ioaddr);
+- tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
+- tx_last = 0;
+- /* Reset the 82595 */
+- eepro_full_reset(ioaddr);
+-}
+-
+-static int read_eeprom(int location)
+-{
+- int i;
+- unsigned short retval = 0;
+- int ee_addr = ioaddr + eeprom_reg;
+- int read_cmd = location | EE_READ_CMD;
+- int ctrl_val = EECS;
+-
+- if (eepro == LAN595FX_10ISA) {
+- eepro_sw2bank1(ioaddr);
+- outb(0x00, ioaddr + STATUS_REG);
+- }
+- eepro_sw2bank2(ioaddr);
+- outb(ctrl_val, ee_addr);
+- /* shift the read command bits out */
+- for (i = 8; i >= 0; i--) {
+- short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
+- outb(outval, ee_addr);
+- outb(outval | EESK, ee_addr); /* EEPROM clock tick */
+- eeprom_delay();
+- outb(outval, ee_addr); /* finish EEPROM clock tick */
+- eeprom_delay();
+- }
+- outb(ctrl_val, ee_addr);
+- for (i = 16; i > 0; i--) {
+- outb(ctrl_val | EESK, ee_addr);
+- eeprom_delay();
+- retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0);
+- outb(ctrl_val, ee_addr);
+- eeprom_delay();
+- }
+- /* terminate the EEPROM access */
+- ctrl_val &= ~EECS;
+- outb(ctrl_val | EESK, ee_addr);
+- eeprom_delay();
+- outb(ctrl_val, ee_addr);
+- eeprom_delay();
+- eepro_sw2bank0(ioaddr);
+- return (retval);
+-}
+-
+-static int eepro_probe1(struct nic *nic)
+-{
+- int i, id, counter, l_eepro = 0;
+- union {
+- unsigned char caddr[ETH_ALEN];
+- unsigned short saddr[ETH_ALEN/2];
+- } station_addr;
+- char *name;
+-
+- id = inb(ioaddr + ID_REG);
+- if ((id & ID_REG_MASK) != ID_REG_SIG)
+- return (0);
+- counter = id & R_ROBIN_BITS;
+- if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40))
+- return (0);
+- /* yes the 82595 has been found */
+- station_addr.saddr[2] = read_eeprom(2);
+- if (station_addr.saddr[2] == 0x0000 || station_addr.saddr[2] == 0xFFFF) {
+- l_eepro = 3;
+- eepro = LAN595FX_10ISA;
+- eeprom_reg= EEPROM_REG_10;
+- rcv_start = RCV_START_10;
+- xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10;
+- xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10;
+- station_addr.saddr[2] = read_eeprom(2);
+- }
+- station_addr.saddr[1] = read_eeprom(3);
+- station_addr.saddr[0] = read_eeprom(4);
+- if (l_eepro)
+- name = "Intel EtherExpress 10 ISA";
+- else if (read_eeprom(7) == ee_FX_INT2IRQ) {
+- name = "Intel EtherExpress Pro/10+ ISA";
+- l_eepro = 2;
+- } else if (station_addr.saddr[0] == SA_ADDR1) {
+- name = "Intel EtherExpress Pro/10 ISA";
+- l_eepro = 1;
+- } else {
+- l_eepro = 0;
+- name = "Intel 82595-based LAN card";
+- }
+- station_addr.saddr[0] = swap16(station_addr.saddr[0]);
+- station_addr.saddr[1] = swap16(station_addr.saddr[1]);
+- station_addr.saddr[2] = swap16(station_addr.saddr[2]);
+- for (i = 0; i < ETH_ALEN; i++) {
+- nic->node_addr[i] = station_addr.caddr[i];
+- }
+- printf("\n%s ioaddr %#hX, addr %!", name, ioaddr, nic->node_addr);
+- mem_start = RCV_LOWER_LIMIT << 8;
+- if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29)
+- mem_end = RCV_UPPER_LIMIT << 8;
+- else {
+- mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8);
+- rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8);
+- }
+- printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10,
+- GetBit(read_eeprom(5), ee_BNC_TPE) ? "BNC" : "TP");
+- return (1);
+-}
+-
+-/**************************************************************************
+-PROBE - Look for an adapter, this routine's visible to the outside
+-***************************************************************************/
+-struct nic *eepro_probe(struct nic *nic, unsigned short *probe_addrs)
+-{
+- unsigned short *p;
+- /* same probe list as the Linux driver */
+- static unsigned short ioaddrs[] = {
+- 0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360, 0};
+-
+- if (probe_addrs == 0 || probe_addrs[0] == 0)
+- probe_addrs = ioaddrs;
+- for (p = probe_addrs; (ioaddr = *p) != 0; p++) {
+- if (eepro_probe1(nic))
+- break;
+- }
+- if (*p == 0)
+- return (0);
+- eepro_reset(nic);
+- /* point to NIC specific routines */
+- nic->reset = eepro_reset;
+- nic->poll = eepro_poll;
+- nic->transmit = eepro_transmit;
+- nic->disable = eepro_disable;
+- return (nic);
+-}
+diff -Naur grub-0.97.orig/netboot/eepro100.c grub-0.97/netboot/eepro100.c
+--- grub-0.97.orig/netboot/eepro100.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/eepro100.c 2005-08-31 19:03:35.000000000 +0000
+@@ -80,8 +80,8 @@
+ *
+ * Caveats:
+ *
+- * The etherboot framework moves the code to the 32k segment from
+- * 0x98000 to 0xa0000. There is just a little room between the end of
++ * The Etherboot framework moves the code to the 48k segment from
++ * 0x94000 to 0xa0000. There is just a little room between the end of
+ * this driver and the 0xa0000 address. If you compile in too many
+ * features, this will overflow.
+ * The number under "hex" in the output of size that scrolls by while
+@@ -92,17 +92,13 @@
+ /* The etherboot authors seem to dislike the argument ordering in
+ * outb macros that Linux uses. I disklike the confusion that this
+ * has caused even more.... This file uses the Linux argument ordering. */
+-/* Sorry not us. It's inherted code from FreeBSD. [The authors] */
++/* Sorry not us. It's inherited code from FreeBSD. [The authors] */
+
+ #include "etherboot.h"
+ #include "nic.h"
+ #include "pci.h"
+-#include "cards.h"
+ #include "timer.h"
+
+-#undef virt_to_bus
+-#define virt_to_bus(x) ((unsigned long)x)
+-
+ static int ioaddr;
+
+ typedef unsigned char u8;
+@@ -121,6 +117,18 @@
+ SCBEarlyRx = 20, /* Early receive byte count. */
+ };
+
++enum SCBCmdBits {
++ SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000,
++ SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400,
++ SCBTriggerIntr=0x0200, SCBMaskAll=0x0100,
++ /* The rest are Rx and Tx commands. */
++ CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, CUShowStats=0x0050,
++ CUCmdBase=0x0060, /* CU Base address (set to zero) . */
++ CUDumpStats=0x0070, /* Dump then reset stats counters. */
++ RxStart=0x0001, RxResume=0x0002, RxAbort=0x0004, RxAddrLoad=0x0006,
++ RxResumeNoResources=0x0007,
++};
++
+ static int do_eeprom_cmd(int cmd, int cmd_len);
+ void hd(void *where, int n);
+
+@@ -139,8 +147,6 @@
+ #define EE_WRITE_1 0x4806
+ #define EE_ENB (0x4800 | EE_CS)
+
+-#define udelay(n) waiton_timer2(((n)*TICKS_PER_MS)/1000)
+-
+ /* The EEPROM commands include the alway-set leading bit. */
+ #define EE_READ_CMD 6
+
+@@ -184,9 +190,18 @@
+ Typically this takes 0 ticks. */
+ static inline void wait_for_cmd_done(int cmd_ioaddr)
+ {
+- short wait = 100;
+- do ;
+- while(inb(cmd_ioaddr) && --wait >= 0);
++ int wait = 0;
++ int delayed_cmd;
++
++ do
++ if (inb(cmd_ioaddr) == 0) return;
++ while(++wait <= 100);
++ delayed_cmd = inb(cmd_ioaddr);
++ do
++ if (inb(cmd_ioaddr) == 0) break;
++ while(++wait <= 10000);
++ printf("Command %2.2x was not immediately accepted, %d ticks!\n",
++ delayed_cmd, wait);
+ }
+
+ /* Elements of the dump_statistics block. This block must be lword aligned. */
+@@ -212,35 +227,30 @@
+
+ /* A speedo3 TX buffer descriptor with two buffers... */
+ static struct TxFD {
+- volatile s16 status;
+- s16 command;
+- u32 link; /* void * */
+- u32 tx_desc_addr; /* (almost) Always points to the tx_buf_addr element. */
+- s32 count; /* # of TBD (=2), Tx start thresh., etc. */
+- /* This constitutes two "TBD" entries: hdr and data */
+- u32 tx_buf_addr0; /* void *, header of frame to be transmitted. */
+- s32 tx_buf_size0; /* Length of Tx hdr. */
+- u32 tx_buf_addr1; /* void *, data to be transmitted. */
+- s32 tx_buf_size1; /* Length of Tx data. */
++ volatile s16 status;
++ s16 command;
++ u32 link; /* void * */
++ u32 tx_desc_addr; /* (almost) Always points to the tx_buf_addr element. */
++ s32 count; /* # of TBD (=2), Tx start thresh., etc. */
++ /* This constitutes two "TBD" entries: hdr and data */
++ u32 tx_buf_addr0; /* void *, header of frame to be transmitted. */
++ s32 tx_buf_size0; /* Length of Tx hdr. */
++ u32 tx_buf_addr1; /* void *, data to be transmitted. */
++ s32 tx_buf_size1; /* Length of Tx data. */
+ } txfd;
+
+ struct RxFD { /* Receive frame descriptor. */
+- volatile s16 status;
+- s16 command;
+- u32 link; /* struct RxFD * */
+- u32 rx_buf_addr; /* void * */
+- u16 count;
+- u16 size;
+- char packet[1518];
++ volatile s16 status;
++ s16 command;
++ u32 link; /* struct RxFD * */
++ u32 rx_buf_addr; /* void * */
++ u16 count;
++ u16 size;
++ char packet[1518];
+ };
+
+-#ifdef USE_LOWMEM_BUFFER
+-#define rxfd ((struct RxFD *)(0x10000 - sizeof(struct RxFD)))
+-#define ACCESS(x) x->
+-#else
+ static struct RxFD rxfd;
+ #define ACCESS(x) x.
+-#endif
+
+ static int congenb = 0; /* Enable congestion control in the DP83840. */
+ static int txfifo = 8; /* Tx FIFO threshold in 4 byte units, 0-15 */
+@@ -256,8 +266,7 @@
+ u32 link;
+ unsigned char data[22];
+ } confcmd = {
+- 0, CmdConfigure,
+- (u32) & txfd,
++ 0, 0, 0, /* filled in later */
+ {22, 0x08, 0, 0, 0, 0x80, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
+ 0, 0x2E, 0, 0x60, 0,
+ 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
+@@ -276,19 +285,20 @@
+
+ static int mdio_write(int phy_id, int location, int value)
+ {
+- int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */
++ int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */
+
+- outl(0x04000000 | (location<<16) | (phy_id<<21) | value,
+- ioaddr + SCBCtrlMDI);
+- do {
+- udelay(16);
+-
+- val = inl(ioaddr + SCBCtrlMDI);
+- if (--boguscnt < 0) {
+- printf(" mdio_write() timed out with val = %X.\n", val);
+- }
+- } while (! (val & 0x10000000));
+- return val & 0xffff;
++ outl(0x04000000 | (location<<16) | (phy_id<<21) | value,
++ ioaddr + SCBCtrlMDI);
++ do {
++ udelay(16);
++
++ val = inl(ioaddr + SCBCtrlMDI);
++ if (--boguscnt < 0) {
++ printf(" mdio_write() timed out with val = %X.\n", val);
++ break;
++ }
++ } while (! (val & 0x10000000));
++ return val & 0xffff;
+ }
+
+ /* Support function: mdio_read
+@@ -298,17 +308,19 @@
+ */
+ static int mdio_read(int phy_id, int location)
+ {
+- int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */
+- outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI);
+- do {
+- udelay(16);
+-
+- val = inl(ioaddr + SCBCtrlMDI);
+- if (--boguscnt < 0) {
+- printf( " mdio_read() timed out with val = %X.\n", val);
+- }
+- } while (! (val & 0x10000000));
+- return val & 0xffff;
++ int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */
++ outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI);
++ do {
++ udelay(16);
++
++ val = inl(ioaddr + SCBCtrlMDI);
++
++ if (--boguscnt < 0) {
++ printf( " mdio_read() timed out with val = %X.\n", val);
++ break;
++ }
++ } while (! (val & 0x10000000));
++ return val & 0xffff;
+ }
+
+ /* The fixes for the code were kindly provided by Dragan Stancevic
+@@ -340,25 +352,26 @@
+ return retval;
+ }
+
++#if 0
+ static inline void whereami (const char *str)
+ {
+-#if 0
+ printf ("%s\n", str);
+ sleep (2);
+-#endif
+ }
++#else
++#define whereami(s)
++#endif
+
+-/* function: eepro100_reset
+- * resets the card. This is used to allow Etherboot to probe the card again
+- * from a "virginal" state....
+- * Arguments: none
+- *
+- * returns: void.
+- */
+-
+-static void eepro100_reset(struct nic *nic)
++static void eepro100_irq(struct nic *nic __unused, irq_action_t action __unused)
+ {
+- outl(0, ioaddr + SCBPort);
++ switch ( action ) {
++ case DISABLE :
++ break;
++ case ENABLE :
++ break;
++ case FORCE :
++ break;
++ }
+ }
+
+ /* function: eepro100_transmit
+@@ -373,61 +386,87 @@
+
+ static void eepro100_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
+ {
+- struct eth_hdr {
+- unsigned char dst_addr[ETH_ALEN];
+- unsigned char src_addr[ETH_ALEN];
+- unsigned short type;
+- } hdr;
+- unsigned short status;
+- int to;
+- int s1, s2;
+-
+- status = inw(ioaddr + SCBStatus);
+- /* Acknowledge all of the current interrupt sources ASAP. */
+- outw(status & 0xfc00, ioaddr + SCBStatus);
++ struct eth_hdr {
++ unsigned char dst_addr[ETH_ALEN];
++ unsigned char src_addr[ETH_ALEN];
++ unsigned short type;
++ } hdr;
++ unsigned short status;
++ int s1, s2;
++
++ status = inw(ioaddr + SCBStatus);
++ /* Acknowledge all of the current interrupt sources ASAP. */
++ outw(status & 0xfc00, ioaddr + SCBStatus);
+
+ #ifdef DEBUG
+- printf ("transmitting type %hX packet (%d bytes). status = %hX, cmd=%hX\n",
+- t, s, status, inw (ioaddr + SCBCmd));
++ printf ("transmitting type %hX packet (%d bytes). status = %hX, cmd=%hX\n",
++ t, s, status, inw (ioaddr + SCBCmd));
+ #endif
+
+- memcpy (&hdr.dst_addr, d, ETH_ALEN);
+- memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
++ memcpy (&hdr.dst_addr, d, ETH_ALEN);
++ memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
+
+- hdr.type = htons (t);
++ hdr.type = htons (t);
+
+- txfd.status = 0;
+- txfd.command = CmdSuspend | CmdTx | CmdTxFlex;
+- txfd.link = virt_to_bus (&txfd);
+- txfd.count = 0x02208000;
+- txfd.tx_desc_addr = (u32)&txfd.tx_buf_addr0;
++ txfd.status = 0;
++ txfd.command = CmdSuspend | CmdTx | CmdTxFlex;
++ txfd.link = virt_to_bus (&txfd);
++ txfd.count = 0x02208000;
++ txfd.tx_desc_addr = virt_to_bus(&txfd.tx_buf_addr0);
+
+- txfd.tx_buf_addr0 = virt_to_bus (&hdr);
+- txfd.tx_buf_size0 = sizeof (hdr);
++ txfd.tx_buf_addr0 = virt_to_bus (&hdr);
++ txfd.tx_buf_size0 = sizeof (hdr);
+
+- txfd.tx_buf_addr1 = virt_to_bus (p);
+- txfd.tx_buf_size1 = s;
++ txfd.tx_buf_addr1 = virt_to_bus (p);
++ txfd.tx_buf_size1 = s;
+
+ #ifdef DEBUG
+- printf ("txfd: \n");
+- hd (&txfd, sizeof (txfd));
++ printf ("txfd: \n");
++ hd (&txfd, sizeof (txfd));
+ #endif
+
+- outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
+- outw(INT_MASK | CU_START, ioaddr + SCBCmd);
+- wait_for_cmd_done(ioaddr + SCBCmd);
+-
+- s1 = inw (ioaddr + SCBStatus);
+- load_timer2(10*TICKS_PER_MS); /* timeout 10 ms for transmit */
+- while (!txfd.status && timer2_running())
+- /* Wait */;
+- s2 = inw (ioaddr + SCBStatus);
++ outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
++ outw(INT_MASK | CU_START, ioaddr + SCBCmd);
++ wait_for_cmd_done(ioaddr + SCBCmd);
++
++ s1 = inw (ioaddr + SCBStatus);
++ load_timer2(10*TICKS_PER_MS); /* timeout 10 ms for transmit */
++ while (!txfd.status && timer2_running())
++ /* Wait */;
++ s2 = inw (ioaddr + SCBStatus);
+
+ #ifdef DEBUG
+- printf ("s1 = %hX, s2 = %hX.\n", s1, s2);
++ printf ("s1 = %hX, s2 = %hX.\n", s1, s2);
+ #endif
+ }
+
++/*
++ * Sometimes the receiver stops making progress. This routine knows how to
++ * get it going again, without losing packets or being otherwise nasty like
++ * a chip reset would be. Previously the driver had a whole sequence
++ * of if RxSuspended, if it's no buffers do one thing, if it's no resources,
++ * do another, etc. But those things don't really matter. Separate logic
++ * in the ISR provides for allocating buffers--the other half of operation
++ * is just making sure the receiver is active. speedo_rx_soft_reset does that.
++ * This problem with the old, more involved algorithm is shown up under
++ * ping floods on the order of 60K packets/second on a 100Mbps fdx network.
++ */
++static void
++speedo_rx_soft_reset(void)
++{
++ wait_for_cmd_done(ioaddr + SCBCmd);
++ /*
++ * Put the hardware into a known state.
++ */
++ outb(RX_ABORT, ioaddr + SCBCmd);
++
++ ACCESS(rxfd)rx_buf_addr = 0xffffffff;
++
++ wait_for_cmd_done(ioaddr + SCBCmd);
++
++ outb(RX_START, ioaddr + SCBCmd);
++}
++
+ /* function: eepro100_poll / eth_poll
+ * This recieves a packet from the network.
+ *
+@@ -440,34 +479,87 @@
+ * returns the length of the packet in nic->packetlen.
+ */
+
+-static int eepro100_poll(struct nic *nic)
++static int eepro100_poll(struct nic *nic, int retrieve)
+ {
+- if (!ACCESS(rxfd)status)
+- return 0;
++ unsigned int status;
++ status = inw(ioaddr + SCBStatus);
+
+- /* Ok. We got a packet. Now restart the reciever.... */
+- ACCESS(rxfd)status = 0;
+- ACCESS(rxfd)command = 0xc000;
+- outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
+- outw(INT_MASK | RX_START, ioaddr + SCBCmd);
+- wait_for_cmd_done(ioaddr + SCBCmd);
++ if (!ACCESS(rxfd)status)
++ return 0;
++
++ /* There is a packet ready */
++ if ( ! retrieve ) return 1;
++
++ /*
++ * The chip may have suspended reception for various reasons.
++ * Check for that, and re-prime it should this be the case.
++ */
++ switch ((status >> 2) & 0xf) {
++ case 0: /* Idle */
++ break;
++ case 1: /* Suspended */
++ case 2: /* No resources (RxFDs) */
++ case 9: /* Suspended with no more RBDs */
++ case 10: /* No resources due to no RBDs */
++ case 12: /* Ready with no RBDs */
++ speedo_rx_soft_reset();
++ break;
++ case 3: case 5: case 6: case 7: case 8:
++ case 11: case 13: case 14: case 15:
++ /* these are all reserved values */
++ break;
++ }
++
++ /* Ok. We got a packet. Now restart the reciever.... */
++ ACCESS(rxfd)status = 0;
++ ACCESS(rxfd)command = 0xc000;
++ outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
++ outw(INT_MASK | RX_START, ioaddr + SCBCmd);
++ wait_for_cmd_done(ioaddr + SCBCmd);
+
+ #ifdef DEBUG
+- printf ("Got a packet: Len = %d.\n", ACCESS(rxfd)count & 0x3fff);
++ printf ("Got a packet: Len = %d.\n", ACCESS(rxfd)count & 0x3fff);
+ #endif
+- nic->packetlen = ACCESS(rxfd)count & 0x3fff;
+- memcpy (nic->packet, ACCESS(rxfd)packet, nic->packetlen);
++ nic->packetlen = ACCESS(rxfd)count & 0x3fff;
++ memcpy (nic->packet, ACCESS(rxfd)packet, nic->packetlen);
+ #ifdef DEBUG
+- hd (nic->packet, 0x30);
++ hd (nic->packet, 0x30);
+ #endif
+- return 1;
++ return 1;
+ }
+
+-static void eepro100_disable(struct nic *nic)
++/* function: eepro100_disable
++ * resets the card. This is used to allow Etherboot or Linux
++ * to probe the card again from a "virginal" state....
++ * Arguments: none
++ *
++ * returns: void.
++ */
++static void eepro100_disable(struct dev *dev __unused)
+ {
+- /* See if this PartialReset solves the problem with interfering with
+- kernel operation after Etherboot hands over. - Ken 20001102 */
+- outl(2, ioaddr + SCBPort);
++/* from eepro100_reset */
++ outl(0, ioaddr + SCBPort);
++/* from eepro100_disable */
++ /* See if this PartialReset solves the problem with interfering with
++ kernel operation after Etherboot hands over. - Ken 20001102 */
++ outl(2, ioaddr + SCBPort);
++
++ /* The following is from the Intel e100 driver.
++ * This hopefully solves the problem with hanging hard DOS images. */
++
++ /* wait for the reset to take effect */
++ udelay(20);
++
++ /* Mask off our interrupt line -- it is unmasked after reset */
++ {
++ u16 intr_status;
++ /* Disable interrupts on our PCI board by setting the mask bit */
++ outw(INT_MASK, ioaddr + SCBCmd);
++ intr_status = inw(ioaddr + SCBStatus);
++ /* ack and clear intrs */
++ outw(intr_status, ioaddr + SCBStatus);
++ inw(ioaddr + SCBStatus);
++ }
+ }
+
+ /* exported function: eepro100_probe / eth_probe
+@@ -478,25 +570,30 @@
+ * leaves the 82557 initialized, and ready to recieve packets.
+ */
+
+-struct nic *eepro100_probe(struct nic *nic, unsigned short *probeaddrs, struct pci_device *p)
++static int eepro100_probe(struct dev *dev, struct pci_device *p)
+ {
++ struct nic *nic = (struct nic *)dev;
+ unsigned short sum = 0;
+ int i;
+ int read_cmd, ee_size;
+- unsigned short value;
+ int options;
+- int promisc;
++ int rx_mode;
+
+ /* we cache only the first few words of the EEPROM data
+ be careful not to access beyond this array */
+ unsigned short eeprom[16];
+
+- if (probeaddrs == 0 || probeaddrs[0] == 0)
++ if (p->ioaddr == 0)
+ return 0;
+- ioaddr = probeaddrs[0] & ~3; /* Mask the bit that says "this is an io addr" */
++ ioaddr = p->ioaddr & ~3; /* Mask the bit that says "this is an io addr" */
++ nic->ioaddr = ioaddr;
+
+ adjust_pci_device(p);
+
++ /* Copy IRQ from PCI information */
++ /* nic->irqno = pci->irq; */
++ nic->irqno = 0;
++
+ if ((do_eeprom_cmd(EE_READ_CMD << 24, 27) & 0xffe0000)
+ == 0xffe0000) {
+ ee_size = 0x100;
+@@ -513,123 +610,138 @@
+ sum += value;
+ }
+
+- for (i=0;i<ETH_ALEN;i++) {
+- nic->node_addr[i] = (eeprom[i/2] >> (8*(i&1))) & 0xff;
+- }
+- printf ("Ethernet addr: %!\n", nic->node_addr);
+-
+- if (sum != 0xBABA)
+- printf("eepro100: Invalid EEPROM checksum %#hX, "
+- "check settings before activating this device!\n", sum);
+- outl(0, ioaddr + SCBPort);
+- udelay (10000);
+-
+- whereami ("Got eeprom.");
+-
+- outl(virt_to_bus(&lstats), ioaddr + SCBPointer);
+- outw(INT_MASK | CU_STATSADDR, ioaddr + SCBCmd);
+- wait_for_cmd_done(ioaddr + SCBCmd);
+-
+- whereami ("set stats addr.");
+- /* INIT RX stuff. */
+-
+- /* Base = 0 */
+- outl(0, ioaddr + SCBPointer);
+- outw(INT_MASK | RX_ADDR_LOAD, ioaddr + SCBCmd);
+- wait_for_cmd_done(ioaddr + SCBCmd);
+-
+- whereami ("set rx base addr.");
+-
+- ACCESS(rxfd)status = 0x0001;
+- ACCESS(rxfd)command = 0x0000;
+- ACCESS(rxfd)link = virt_to_bus(&(ACCESS(rxfd)status));
+- ACCESS(rxfd)rx_buf_addr = (int) &nic->packet;
+- ACCESS(rxfd)count = 0;
+- ACCESS(rxfd)size = 1528;
+-
+- outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
+- outw(INT_MASK | RX_START, ioaddr + SCBCmd);
+- wait_for_cmd_done(ioaddr + SCBCmd);
+-
+- whereami ("started RX process.");
+-
+- /* Start the reciever.... */
+- ACCESS(rxfd)status = 0;
+- ACCESS(rxfd)command = 0xc000;
+- outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
+- outw(INT_MASK | RX_START, ioaddr + SCBCmd);
+-
+- /* INIT TX stuff. */
+-
+- /* Base = 0 */
+- outl(0, ioaddr + SCBPointer);
+- outw(INT_MASK | CU_CMD_BASE, ioaddr + SCBCmd);
+- wait_for_cmd_done(ioaddr + SCBCmd);
+-
+- whereami ("set TX base addr.");
+-
+- txfd.command = (CmdIASetup);
+- txfd.status = 0x0000;
+- txfd.link = virt_to_bus (&confcmd);
+-
+- {
+- char *t = (char *)&txfd.tx_desc_addr;
++ for (i=0;i<ETH_ALEN;i++) {
++ nic->node_addr[i] = (eeprom[i/2] >> (8*(i&1))) & 0xff;
++ }
++ printf ("Ethernet addr: %!\n", nic->node_addr);
+
+- for (i=0;i<ETH_ALEN;i++)
+- t[i] = nic->node_addr[i];
+- }
++ if (sum != 0xBABA)
++ printf("eepro100: Invalid EEPROM checksum %#hX, "
++ "check settings before activating this device!\n", sum);
++ outl(0, ioaddr + SCBPort);
++ udelay (10000);
++ whereami ("Got eeprom.");
++
++ /* Base = 0 */
++ outl(0, ioaddr + SCBPointer);
++ outw(INT_MASK | RX_ADDR_LOAD, ioaddr + SCBCmd);
++ wait_for_cmd_done(ioaddr + SCBCmd);
++ whereami ("set rx base addr.");
++
++ outl(virt_to_bus(&lstats), ioaddr + SCBPointer);
++ outw(INT_MASK | CU_STATSADDR, ioaddr + SCBCmd);
++ wait_for_cmd_done(ioaddr + SCBCmd);
++ whereami ("set stats addr.");
++
++ /* INIT RX stuff. */
++ ACCESS(rxfd)status = 0x0001;
++ ACCESS(rxfd)command = 0x0000;
++ ACCESS(rxfd)link = virt_to_bus(&(ACCESS(rxfd)status));
++ ACCESS(rxfd)rx_buf_addr = virt_to_bus(&nic->packet);
++ ACCESS(rxfd)count = 0;
++ ACCESS(rxfd)size = 1528;
++
++ outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
++ outw(INT_MASK | RX_START, ioaddr + SCBCmd);
++ wait_for_cmd_done(ioaddr + SCBCmd);
++
++ whereami ("started RX process.");
++
++ /* Start the reciever.... */
++ ACCESS(rxfd)status = 0;
++ ACCESS(rxfd)command = 0xc000;
++ outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
++ outw(INT_MASK | RX_START, ioaddr + SCBCmd);
++
++ /* INIT TX stuff. */
++
++ /* Base = 0 */
++ outl(0, ioaddr + SCBPointer);
++ outw(INT_MASK | CU_CMD_BASE, ioaddr + SCBCmd);
++ wait_for_cmd_done(ioaddr + SCBCmd);
++
++ whereami ("set TX base addr.");
++
++ txfd.command = (CmdIASetup);
++ txfd.status = 0x0000;
++ txfd.link = virt_to_bus (&confcmd);
++
++ {
++ char *t = (char *)&txfd.tx_desc_addr;
++
++ for (i=0;i<ETH_ALEN;i++)
++ t[i] = nic->node_addr[i];
++ }
+
+ #ifdef DEBUG
+- printf ("Setup_eaddr:\n");
+- hd (&txfd, 0x20);
++ printf ("Setup_eaddr:\n");
++ hd (&txfd, 0x20);
+ #endif
+- /* options = 0x40; */ /* 10mbps half duplex... */
+- options = 0x00; /* Autosense */
+-
+- promisc = 0;
+-
+- if ( ((eeprom[6]>>8) & 0x3f) == DP83840
+- || ((eeprom[6]>>8) & 0x3f) == DP83840A) {
+- int mdi_reg23 = mdio_read(eeprom[6] & 0x1f, 23) | 0x0422;
+- if (congenb)
+- mdi_reg23 |= 0x0100;
+- printf(" DP83840 specific setup, setting register 23 to %hX.\n",
+- mdi_reg23);
+- mdio_write(eeprom[6] & 0x1f, 23, mdi_reg23);
+- }
+- whereami ("Done DP8340 special setup.");
+- if (options != 0) {
+- mdio_write(eeprom[6] & 0x1f, 0,
+- ((options & 0x20) ? 0x2000 : 0) | /* 100mbps? */
+- ((options & 0x10) ? 0x0100 : 0)); /* Full duplex? */
+- whereami ("set mdio_register.");
+- }
++ /* options = 0x40; */ /* 10mbps half duplex... */
++ options = 0x00; /* Autosense */
+
+- confcmd.command = CmdSuspend | CmdConfigure;
+- confcmd.status = 0x0000;
+- confcmd.link = virt_to_bus (&txfd);
+- confcmd.data[1] = (txfifo << 4) | rxfifo;
+- confcmd.data[4] = rxdmacount;
+- confcmd.data[5] = txdmacount + 0x80;
+- confcmd.data[15] = promisc ? 0x49: 0x48;
+- confcmd.data[19] = (options & 0x10) ? 0xC0 : 0x80;
+- confcmd.data[21] = promisc ? 0x0D: 0x05;
++#ifdef PROMISC
++ rx_mode = 3;
++#elif ALLMULTI
++ rx_mode = 1;
++#else
++ rx_mode = 0;
++#endif
+
+- outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
+- outw(INT_MASK | CU_START, ioaddr + SCBCmd);
+- wait_for_cmd_done(ioaddr + SCBCmd);
++ if ( ((eeprom[6]>>8) & 0x3f) == DP83840
++ || ((eeprom[6]>>8) & 0x3f) == DP83840A) {
++ int mdi_reg23 = mdio_read(eeprom[6] & 0x1f, 23) | 0x0422;
++ if (congenb)
++ mdi_reg23 |= 0x0100;
++ printf(" DP83840 specific setup, setting register 23 to %hX.\n",
++ mdi_reg23);
++ mdio_write(eeprom[6] & 0x1f, 23, mdi_reg23);
++ }
++ whereami ("Done DP8340 special setup.");
++ if (options != 0) {
++ mdio_write(eeprom[6] & 0x1f, 0,
++ ((options & 0x20) ? 0x2000 : 0) | /* 100mbps? */
++ ((options & 0x10) ? 0x0100 : 0)); /* Full duplex? */
++ whereami ("set mdio_register.");
++ }
+
+- whereami ("started TX thingy (config, iasetup).");
++ confcmd.command = CmdSuspend | CmdConfigure;
++ confcmd.status = 0x0000;
++ confcmd.link = virt_to_bus (&txfd);
++ confcmd.data[1] = (txfifo << 4) | rxfifo;
++ confcmd.data[4] = rxdmacount;
++ confcmd.data[5] = txdmacount + 0x80;
++ confcmd.data[15] = (rx_mode & 2) ? 0x49: 0x48;
++ confcmd.data[19] = (options & 0x10) ? 0xC0 : 0x80;
++ confcmd.data[21] = (rx_mode & 1) ? 0x0D: 0x05;
++
++ outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
++ outw(INT_MASK | CU_START, ioaddr + SCBCmd);
++ wait_for_cmd_done(ioaddr + SCBCmd);
++
++ whereami ("started TX thingy (config, iasetup).");
++
++ load_timer2(10*TICKS_PER_MS);
++ while (!txfd.status && timer2_running())
++ /* Wait */;
++
++ /* Read the status register once to disgard stale data */
++ mdio_read(eeprom[6] & 0x1f, 1);
++ /* Check to see if the network cable is plugged in.
++ * This allows for faster failure if there is nothing
++ * we can do.
++ */
++ if (!(mdio_read(eeprom[6] & 0x1f, 1) & (1 << 2))) {
++ printf("Valid link not established\n");
++ eepro100_disable(dev);
++ return 0;
++ }
+
+- load_timer2(10*TICKS_PER_MS);
+- while (!txfd.status && timer2_running())
+- /* Wait */;
+-
+- nic->reset = eepro100_reset;
+- nic->poll = eepro100_poll;
+- nic->transmit = eepro100_transmit;
+- nic->disable = eepro100_disable;
+- return nic;
++ dev->disable = eepro100_disable;
++ nic->poll = eepro100_poll;
++ nic->transmit = eepro100_transmit;
++ nic->irq = eepro100_irq;
++ return 1;
+ }
+
+ /*********************************************************************/
+@@ -639,16 +751,59 @@
+ /* Hexdump a number of bytes from memory... */
+ void hd (void *where, int n)
+ {
+- int i;
++ int i;
+
+- while (n > 0) {
+- printf ("%X ", where);
+- for (i=0;i < ( (n>16)?16:n);i++)
+- printf (" %hhX", ((char *)where)[i]);
+- printf ("\n");
+- n -= 16;
+- where += 16;
+- }
++ while (n > 0) {
++ printf ("%X ", where);
++ for (i=0;i < ( (n>16)?16:n);i++)
++ printf (" %hhX", ((char *)where)[i]);
++ printf ("\n");
++ n -= 16;
++ where += 16;
++ }
+ }
+ #endif
+
++static struct pci_id eepro100_nics[] = {
++PCI_ROM(0x8086, 0x1029, "id1029", "Intel EtherExpressPro100 ID1029"),
++PCI_ROM(0x8086, 0x1030, "id1030", "Intel EtherExpressPro100 ID1030"),
++PCI_ROM(0x8086, 0x1031, "82801cam", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
++PCI_ROM(0x8086, 0x1032, "eepro100-1032", "Intel PRO/100 VE Network Connection"),
++PCI_ROM(0x8086, 0x1033, "eepro100-1033", "Intel PRO/100 VM Network Connection"),
++PCI_ROM(0x8086, 0x1034, "eepro100-1034", "Intel PRO/100 VM Network Connection"),
++PCI_ROM(0x8086, 0x1035, "eepro100-1035", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
++PCI_ROM(0x8086, 0x1036, "eepro100-1036", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
++PCI_ROM(0x8086, 0x1037, "eepro100-1037", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
++PCI_ROM(0x8086, 0x1038, "id1038", "Intel PRO/100 VM Network Connection"),
++PCI_ROM(0x8086, 0x1039, "82562et", "Intel PRO100 VE 82562ET"),
++PCI_ROM(0x8086, 0x103a, "id103a", "Intel Corporation 82559 InBusiness 10/100"),
++PCI_ROM(0x8086, 0x103b, "82562etb", "Intel PRO100 VE 82562ETB"),
++PCI_ROM(0x8086, 0x103c, "eepro100-103c", "Intel PRO/100 VM Network Connection"),
++PCI_ROM(0x8086, 0x103d, "eepro100-103d", "Intel PRO/100 VE Network Connection"),
++PCI_ROM(0x8086, 0x103e, "eepro100-103e", "Intel PRO/100 VM Network Connection"),
++PCI_ROM(0x8086, 0x1059, "82551qm", "Intel PRO/100 M Mobile Connection"),
++PCI_ROM(0x8086, 0x1209, "82559er", "Intel EtherExpressPro100 82559ER"),
++PCI_ROM(0x8086, 0x1227, "82865", "Intel 82865 EtherExpress PRO/100A"),
++PCI_ROM(0x8086, 0x1228, "82556", "Intel 82556 EtherExpress PRO/100 Smart"),
++PCI_ROM(0x8086, 0x1229, "eepro100", "Intel EtherExpressPro100"),
++PCI_ROM(0x8086, 0x2449, "82562em", "Intel EtherExpressPro100 82562EM"),
++PCI_ROM(0x8086, 0x2459, "82562-1", "Intel 82562 based Fast Ethernet Connection"),
++PCI_ROM(0x8086, 0x245d, "82562-2", "Intel 82562 based Fast Ethernet Connection"),
++PCI_ROM(0x8086, 0x1050, "82562ez", "Intel 82562EZ Network Connection"),
++PCI_ROM(0x8086, 0x5200, "eepro100-5200", "Intel EtherExpress PRO/100 Intelligent Server"),
++PCI_ROM(0x8086, 0x5201, "eepro100-5201", "Intel EtherExpress PRO/100 Intelligent Server"),
++};
++
++/* Cards with device ids 0x1030 to 0x103F, 0x2449, 0x2459 or 0x245D might need
++ * a workaround for hardware bug on 10 mbit half duplex (see linux driver eepro100.c)
++ * 2003/03/17 gbaum */
++
++
++struct pci_driver eepro100_driver = {
++ .type = NIC_DRIVER,
++ .name = "EEPRO100",
++ .probe = eepro100_probe,
++ .ids = eepro100_nics,
++ .id_count = sizeof(eepro100_nics)/sizeof(eepro100_nics[0]),
++ .class = 0
++};
+diff -Naur grub-0.97.orig/netboot/elf.h grub-0.97/netboot/elf.h
+--- grub-0.97.orig/netboot/elf.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/elf.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,234 @@
++#ifndef ELF_H
++#define ELF_H
++
++#define EI_NIDENT 16 /* Size of e_ident array. */
++
++/* Values for e_type. */
++#define ET_NONE 0 /* No file type */
++#define ET_REL 1 /* Relocatable file */
++#define ET_EXEC 2 /* Executable file */
++#define ET_DYN 3 /* Shared object file */
++#define ET_CORE 4 /* Core file */
++
++/* Values for e_machine (architecute). */
++#define EM_NONE 0 /* No machine */
++#define EM_M32 1 /* AT&T WE 32100 */
++#define EM_SPARC 2 /* SUN SPARC */
++#define EM_386 3 /* Intel 80386+ */
++#define EM_68K 4 /* Motorola m68k family */
++#define EM_88K 5 /* Motorola m88k family */
++#define EM_486 6 /* Perhaps disused */
++#define EM_860 7 /* Intel 80860 */
++#define EM_MIPS 8 /* MIPS R3000 big-endian */
++#define EM_S370 9 /* IBM System/370 */
++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */
++
++#define EM_PARISC 15 /* HPPA */
++#define EM_VPP500 17 /* Fujitsu VPP500 */
++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */
++#define EM_960 19 /* Intel 80960 */
++#define EM_PPC 20 /* PowerPC */
++#define EM_PPC64 21 /* PowerPC 64-bit */
++#define EM_S390 22 /* IBM S390 */
++
++#define EM_V800 36 /* NEC V800 series */
++#define EM_FR20 37 /* Fujitsu FR20 */
++#define EM_RH32 38 /* TRW RH-32 */
++#define EM_RCE 39 /* Motorola RCE */
++#define EM_ARM 40 /* ARM */
++#define EM_FAKE_ALPHA 41 /* Digital Alpha */
++#define EM_SH 42 /* Hitachi SH */
++#define EM_SPARCV9 43 /* SPARC v9 64-bit */
++#define EM_TRICORE 44 /* Siemens Tricore */
++#define EM_ARC 45 /* Argonaut RISC Core */
++#define EM_H8_300 46 /* Hitachi H8/300 */
++#define EM_H8_300H 47 /* Hitachi H8/300H */
++#define EM_H8S 48 /* Hitachi H8S */
++#define EM_H8_500 49 /* Hitachi H8/500 */
++#define EM_IA_64 50 /* Intel Merced */
++#define EM_MIPS_X 51 /* Stanford MIPS-X */
++#define EM_COLDFIRE 52 /* Motorola Coldfire */
++#define EM_68HC12 53 /* Motorola M68HC12 */
++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/
++#define EM_PCP 55 /* Siemens PCP */
++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */
++#define EM_NDR1 57 /* Denso NDR1 microprocessor */
++#define EM_STARCORE 58 /* Motorola Start*Core processor */
++#define EM_ME16 59 /* Toyota ME16 processor */
++#define EM_ST100 60 /* STMicroelectronic ST100 processor */
++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/
++#define EM_X86_64 62 /* AMD x86-64 architecture */
++#define EM_PDSP 63 /* Sony DSP Processor */
++
++#define EM_FX66 66 /* Siemens FX66 microcontroller */
++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */
++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */
++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */
++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */
++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */
++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */
++#define EM_SVX 73 /* Silicon Graphics SVx */
++#define EM_AT19 74 /* STMicroelectronics ST19 8 bit mc */
++#define EM_VAX 75 /* Digital VAX */
++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */
++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */
++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */
++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */
++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */
++#define EM_HUANY 81 /* Harvard University machine-independent object files */
++#define EM_PRISM 82 /* SiTera Prism */
++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */
++#define EM_FR30 84 /* Fujitsu FR30 */
++#define EM_D10V 85 /* Mitsubishi D10V */
++#define EM_D30V 86 /* Mitsubishi D30V */
++#define EM_V850 87 /* NEC v850 */
++#define EM_M32R 88 /* Mitsubishi M32R */
++#define EM_MN10300 89 /* Matsushita MN10300 */
++#define EM_MN10200 90 /* Matsushita MN10200 */
++#define EM_PJ 91 /* picoJava */
++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
++#define EM_NUM 95
++
++/* Values for p_type. */
++#define PT_NULL 0 /* Unused entry. */
++#define PT_LOAD 1 /* Loadable segment. */
++#define PT_DYNAMIC 2 /* Dynamic linking information segment. */
++#define PT_INTERP 3 /* Pathname of interpreter. */
++#define PT_NOTE 4 /* Auxiliary information. */
++#define PT_SHLIB 5 /* Reserved (not used). */
++#define PT_PHDR 6 /* Location of program header itself. */
++
++/* Values for p_flags. */
++#define PF_X 0x1 /* Executable. */
++#define PF_W 0x2 /* Writable. */
++#define PF_R 0x4 /* Readable. */
++
++
++#define ELF_PROGRAM_RETURNS_BIT 0x8000000 /* e_flags bit 31 */
++
++#define EI_MAG0 0
++#define ELFMAG0 0x7f
++
++#define EI_MAG1 1
++#define ELFMAG1 'E'
++
++#define EI_MAG2 2
++#define ELFMAG2 'L'
++
++#define EI_MAG3 3
++#define ELFMAG3 'F'
++
++#define ELFMAG "\177ELF"
++
++#define EI_CLASS 4 /* File class byte index */
++#define ELFCLASSNONE 0 /* Invalid class */
++#define ELFCLASS32 1 /* 32-bit objects */
++#define ELFCLASS64 2 /* 64-bit objects */
++
++#define EI_DATA 5 /* Data encodeing byte index */
++#define ELFDATANONE 0 /* Invalid data encoding */
++#define ELFDATA2LSB 1 /* 2's complement little endian */
++#define ELFDATA2MSB 2 /* 2's complement big endian */
++
++#define EI_VERSION 6 /* File version byte index */
++ /* Value must be EV_CURRENT */
++
++#define EV_NONE 0 /* Invalid ELF Version */
++#define EV_CURRENT 1 /* Current version */
++
++#define ELF32_PHDR_SIZE (8*4) /* Size of an elf program header */
++
++#ifndef ASSEMBLY
++/*
++ * ELF definitions common to all 32-bit architectures.
++ */
++
++typedef uint32_t Elf32_Addr;
++typedef uint16_t Elf32_Half;
++typedef uint32_t Elf32_Off;
++typedef int32_t Elf32_Sword;
++typedef uint32_t Elf32_Word;
++typedef uint32_t Elf32_Size;
++
++typedef uint64_t Elf64_Addr;
++typedef uint16_t Elf64_Half;
++typedef uint64_t Elf64_Off;
++typedef int32_t Elf64_Sword;
++typedef uint32_t Elf64_Word;
++typedef uint64_t Elf64_Size;
++
++/*
++ * ELF header.
++ */
++typedef struct {
++ unsigned char e_ident[EI_NIDENT]; /* File identification. */
++ Elf32_Half e_type; /* File type. */
++ Elf32_Half e_machine; /* Machine architecture. */
++ Elf32_Word e_version; /* ELF format version. */
++ Elf32_Addr e_entry; /* Entry point. */
++ Elf32_Off e_phoff; /* Program header file offset. */
++ Elf32_Off e_shoff; /* Section header file offset. */
++ Elf32_Word e_flags; /* Architecture-specific flags. */
++ Elf32_Half e_ehsize; /* Size of ELF header in bytes. */
++ Elf32_Half e_phentsize; /* Size of program header entry. */
++ Elf32_Half e_phnum; /* Number of program header entries. */
++ Elf32_Half e_shentsize; /* Size of section header entry. */
++ Elf32_Half e_shnum; /* Number of section header entries. */
++ Elf32_Half e_shstrndx; /* Section name strings section. */
++} Elf32_Ehdr;
++
++typedef struct {
++ unsigned char e_ident[EI_NIDENT]; /* File identification. */
++ Elf64_Half e_type; /* File type. */
++ Elf64_Half e_machine; /* Machine architecture. */
++ Elf64_Word e_version; /* ELF format version. */
++ Elf64_Addr e_entry; /* Entry point. */
++ Elf64_Off e_phoff; /* Program header file offset. */
++ Elf64_Off e_shoff; /* Section header file offset. */
++ Elf64_Word e_flags; /* Architecture-specific flags. */
++ Elf64_Half e_ehsize; /* Size of ELF header in bytes. */
++ Elf64_Half e_phentsize; /* Size of program header entry. */
++ Elf64_Half e_phnum; /* Number of program header entries. */
++ Elf64_Half e_shentsize; /* Size of section header entry. */
++ Elf64_Half e_shnum; /* Number of section header entries. */
++ Elf64_Half e_shstrndx; /* Section name strings section. */
++} Elf64_Ehdr;
++
++/*
++ * Program header.
++ */
++typedef struct {
++ Elf32_Word p_type; /* Entry type. */
++ Elf32_Off p_offset; /* File offset of contents. */
++ Elf32_Addr p_vaddr; /* Virtual address (not used). */
++ Elf32_Addr p_paddr; /* Physical address. */
++ Elf32_Size p_filesz; /* Size of contents in file. */
++ Elf32_Size p_memsz; /* Size of contents in memory. */
++ Elf32_Word p_flags; /* Access permission flags. */
++ Elf32_Size p_align; /* Alignment in memory and file. */
++} Elf32_Phdr;
++
++typedef struct {
++ Elf64_Word p_type; /* Entry type. */
++ Elf64_Word p_flags; /* Access permission flags. */
++ Elf64_Off p_offset; /* File offset of contents. */
++ Elf64_Addr p_vaddr; /* Virtual address (not used). */
++ Elf64_Addr p_paddr; /* Physical address. */
++ Elf64_Size p_filesz; /* Size of contents in file. */
++ Elf64_Size p_memsz; /* Size of contents in memory. */
++ Elf64_Size p_align; /* Alignment in memory and file. */
++} Elf64_Phdr;
++
++/* Standardized Elf image notes for booting... The name for all of these is ELFBoot */
++
++
++/* ELF Defines for the current architecture */
++#include "i386_elf.h"
++
++#endif /* ASSEMBLY */
++
++//#include "elf_boot.h"
++
++#endif /* ELF_H */
+diff -Naur grub-0.97.orig/netboot/endian.h grub-0.97/netboot/endian.h
+--- grub-0.97.orig/netboot/endian.h 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/endian.h 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,19 @@
++#ifndef ETHERBOOT_ENDIAN_H
++#define ETHERBOOT_ENDIAN_H
++
++/* Definitions for byte order, according to significance of bytes,
++ from low addresses to high addresses. The value is what you get by
++ putting '4' in the most significant byte, '3' in the second most
++ significant byte, '2' in the second least significant byte, and '1'
++ in the least significant byte, and then writing down one digit for
++ each byte, starting with the byte at the lowest address at the left,
++ and proceeding to the byte with the highest address at the right. */
++
++#define __LITTLE_ENDIAN 1234
++#define __BIG_ENDIAN 4321
++#define __PDP_ENDIAN 3412
++
++#include "i386_endian.h"
++
++
++#endif /* ETHERBOOT_ENDIAN_H */
+diff -Naur grub-0.97.orig/netboot/epic100.c grub-0.97/netboot/epic100.c
+--- grub-0.97.orig/netboot/epic100.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/epic100.c 2005-08-31 19:03:35.000000000 +0000
+@@ -1,15 +1,18 @@
++
+ /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
+
++/* 05/06/2003 timlegge Fixed relocation and implemented Multicast */
+ #define LINUX_OUT_MACROS
+
+ #include "etherboot.h"
++#include "pci.h"
+ #include "nic.h"
+-#include "cards.h"
+ #include "timer.h"
+ #include "epic100.h"
+
+-#undef virt_to_bus
+-#define virt_to_bus(x) ((unsigned long)x)
++/* Condensed operations for readability */
++#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
++#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
+
+ #define TX_RING_SIZE 2 /* use at least 2 buffers for TX */
+ #define RX_RING_SIZE 2
+@@ -26,23 +29,18 @@
+
+ /* The EPIC100 Rx and Tx buffer descriptors. */
+ struct epic_rx_desc {
+- unsigned short status;
+- unsigned short rxlength;
+- unsigned long bufaddr;
+- unsigned short buflength;
+- unsigned short control;
+- unsigned long next;
++ unsigned long status;
++ unsigned long bufaddr;
++ unsigned long buflength;
++ unsigned long next;
+ };
+-
+ /* description of the tx descriptors control bits commonly used */
+ #define TD_STDFLAGS TD_LASTDESC
+
+ struct epic_tx_desc {
+- unsigned short status;
+- unsigned short txlength;
+- unsigned long bufaddr;
+- unsigned short buflength;
+- unsigned short control;
++ unsigned long status;
++ unsigned long bufaddr;
++ unsigned long buflength;
+ unsigned long next;
+ };
+
+@@ -51,12 +49,15 @@
+
+ static void epic100_open(void);
+ static void epic100_init_ring(void);
+-static void epic100_disable(struct nic *nic);
+-static int epic100_poll(struct nic *nic);
++static void epic100_disable(struct dev *dev);
++static int epic100_poll(struct nic *nic, int retrieve);
+ static void epic100_transmit(struct nic *nic, const char *destaddr,
+ unsigned int type, unsigned int len, const char *data);
++#ifdef DEBUG_EEPROM
+ static int read_eeprom(int location);
++#endif
+ static int mii_read(int phy_id, int location);
++static void epic100_irq(struct nic *nic, irq_action_t action);
+
+ static int ioaddr;
+
+@@ -69,6 +70,7 @@
+ static int mmctl ;
+ static int mmdata ;
+ static int lan0 ;
++static int mc0 ;
+ static int rxcon ;
+ static int txcon ;
+ static int prcdar ;
+@@ -80,37 +82,27 @@
+ static unsigned short eeprom[64];
+ #endif
+ static signed char phys[4]; /* MII device addresses. */
+-static struct epic_rx_desc rx_ring[RX_RING_SIZE];
+-static struct epic_tx_desc tx_ring[TX_RING_SIZE];
+-#ifdef USE_LOWMEM_BUFFER
+-#define rx_packet ((char *)0x10000 - PKT_BUF_SZ * RX_RING_SIZE)
+-#define tx_packet ((char *)0x10000 - PKT_BUF_SZ * RX_RING_SIZE - PKT_BUF_SZ * TX_RING_SIZE)
+-#else
+-static char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
+-static char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
+-#endif
++static struct epic_rx_desc rx_ring[RX_RING_SIZE]
++ __attribute__ ((aligned(4)));
++static struct epic_tx_desc tx_ring[TX_RING_SIZE]
++ __attribute__ ((aligned(4)));
++static unsigned char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
++static unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
+
+ /***********************************************************************/
+ /* Externally visible functions */
+ /***********************************************************************/
+
+- static void
+-epic100_reset(struct nic *nic)
+-{
+- /* Soft reset the chip. */
+- outl(GC_SOFT_RESET, genctl);
+-}
+
+- struct nic*
+-epic100_probe(struct nic *nic, unsigned short *probeaddrs)
++ static int
++epic100_probe(struct dev *dev, struct pci_device *pci)
+ {
+- unsigned short sum = 0;
+- unsigned short value;
++ struct nic *nic = (struct nic *)dev;
+ int i;
+ unsigned short* ap;
+ unsigned int phy, phy_idx;
+
+- if (probeaddrs == 0 || probeaddrs[0] == 0)
++ if (pci->ioaddr == 0)
+ return 0;
+
+ /* Ideally we would detect all network cards in slot order. That would
+@@ -118,7 +110,9 @@
+ well with the current structure. So instead we detect just the
+ Epic cards in slot order. */
+
+- ioaddr = probeaddrs[0] & ~3; /* Mask the bit that says "this is an io addr" */
++ ioaddr = pci->ioaddr;
++ nic->irqno = 0;
++ nic->ioaddr = pci->ioaddr & ~3;
+
+ /* compute all used static epic100 registers address */
+ command = ioaddr + COMMAND; /* Control Register */
+@@ -130,6 +124,7 @@
+ mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
+ mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
+ lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
++ mc0 = ioaddr + MC0; /* Multicast Control */
+ rxcon = ioaddr + RXCON; /* Receive Control */
+ txcon = ioaddr + TXCON; /* Transmit Control */
+ prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
+@@ -160,11 +155,15 @@
+ }
+
+ #ifdef DEBUG_EEPROM
++{
++ unsigned short sum = 0;
++ unsigned short value;
+ for (i = 0; i < 64; i++) {
+ value = read_eeprom(i);
+ eeprom[i] = value;
+ sum += value;
+ }
++}
+
+ #if (EPIC_DEBUG > 1)
+ printf("EEPROM contents\n");
+@@ -202,15 +201,26 @@
+
+ epic100_open();
+
+- nic->reset = epic100_reset;
++ dev->disable = epic100_disable;
+ nic->poll = epic100_poll;
+ nic->transmit = epic100_transmit;
+- nic->disable = epic100_disable;
++ nic->irq = epic100_irq;
+
+- return nic;
++ return 1;
+ }
+
+- static void
++static void set_rx_mode(void)
++{
++ unsigned char mc_filter[8];
++ int i;
++ memset(mc_filter, 0xff, sizeof(mc_filter));
++ outl(0x0C, rxcon);
++ for(i = 0; i < 4; i++)
++ outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
++ return;
++}
++
++ static void
+ epic100_open(void)
+ {
+ int mii_reg5;
+@@ -237,11 +247,11 @@
+ outl(tmp, txcon);
+
+ /* Give adress of RX and TX ring to the chip */
+- outl(virt_to_bus(&rx_ring), prcdar);
+- outl(virt_to_bus(&tx_ring), ptcdar);
++ outl(virt_to_le32desc(&rx_ring), prcdar);
++ outl(virt_to_le32desc(&tx_ring), ptcdar);
+
+ /* Start the chip's Rx process: receive unicast and broadcast */
+- outl(0x04, rxcon);
++ set_rx_mode();
+ outl(CR_START_RX | CR_QUEUE_RX, command);
+
+ putchar('\n');
+@@ -252,34 +262,30 @@
+ epic100_init_ring(void)
+ {
+ int i;
+- char* p;
+
+ cur_rx = cur_tx = 0;
+
+- p = &rx_packet[0];
+ for (i = 0; i < RX_RING_SIZE; i++) {
+- rx_ring[i].status = RRING_OWN; /* Owned by Epic chip */
+- rx_ring[i].buflength = PKT_BUF_SZ;
+- rx_ring[i].bufaddr = virt_to_bus(p + (PKT_BUF_SZ * i));
+- rx_ring[i].control = 0;
+- rx_ring[i].next = virt_to_bus(&(rx_ring[i + 1]) );
++ rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */
++ rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
++ rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
++ rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ;
+ }
+ /* Mark the last entry as wrapping the ring. */
+- rx_ring[i-1].next = virt_to_bus(&rx_ring[0]);
++ rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
+
+ /*
+ *The Tx buffer descriptor is filled in as needed,
+ * but we do need to clear the ownership bit.
+ */
+- p = &tx_packet[0];
+
+ for (i = 0; i < TX_RING_SIZE; i++) {
+- tx_ring[i].status = 0; /* Owned by CPU */
+- tx_ring[i].bufaddr = virt_to_bus(p + (PKT_BUF_SZ * i));
+- tx_ring[i].control = TD_STDFLAGS;
+- tx_ring[i].next = virt_to_bus(&(tx_ring[i + 1]) );
++ tx_ring[i].status = 0x0000; /* Owned by CPU */
++ tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
++ tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
++ tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]);
+ }
+- tx_ring[i-1].next = virt_to_bus(&tx_ring[0]);
++ tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]);
+ }
+
+ /* function: epic100_transmit
+@@ -296,7 +302,7 @@
+ unsigned int len, const char *data)
+ {
+ unsigned short nstype;
+- char* txp;
++ unsigned char *txp;
+ int entry;
+
+ /* Calculate the next Tx descriptor entry. */
+@@ -310,7 +316,7 @@
+ return;
+ }
+
+- txp = (char*)tx_ring[entry].bufaddr;
++ txp = tx_packet + (entry * PKT_BUF_SZ);
+
+ memcpy(txp, destaddr, ETH_ALEN);
+ memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
+@@ -319,26 +325,29 @@
+ memcpy(txp + ETH_HLEN, data, len);
+
+ len += ETH_HLEN;
+-
++ len &= 0x0FFF;
++ while(len < ETH_ZLEN)
++ txp[len++] = '\0';
+ /*
+ * Caution: the write order is important here,
+ * set the base address with the "ownership"
+ * bits last.
+ */
+- tx_ring[entry].txlength = (len >= 60 ? len : 60);
+- tx_ring[entry].buflength = len;
+- tx_ring[entry].status = TRING_OWN; /* Pass ownership to the chip. */
++
++ tx_ring[entry].buflength |= cpu_to_le32(len);
++ tx_ring[entry].status = cpu_to_le32(len << 16) |
++ cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */
+
+ cur_tx++;
+
+ /* Trigger an immediate transmit demand. */
+- outl(CR_QUEUE_TX, command);
+-
++ outl(CR_QUEUE_TX, command);
++
+ load_timer2(10*TICKS_PER_MS); /* timeout 10 ms for transmit */
+- while ((tx_ring[entry].status & TRING_OWN) && timer2_running())
++ while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) && timer2_running())
+ /* Wait */;
+
+- if ((tx_ring[entry].status & TRING_OWN) != 0)
++ if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
+ printf("Oops, transmitter timeout, status=%hX\n",
+ tx_ring[entry].status);
+ }
+@@ -356,17 +365,19 @@
+ */
+
+ static int
+-epic100_poll(struct nic *nic)
++epic100_poll(struct nic *nic, int retrieve)
+ {
+ int entry;
+- int status;
+ int retcode;
+-
++ int status;
+ entry = cur_rx % RX_RING_SIZE;
+
+- if ((status = rx_ring[entry].status & RRING_OWN) == RRING_OWN)
++ if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
+ return (0);
+
++ if ( ! retrieve ) return 1;
++
++ status = le32_to_cpu(rx_ring[entry].status);
+ /* We own the next entry, it's a new packet. Send it up. */
+
+ #if (EPIC_DEBUG > 4)
+@@ -383,8 +394,8 @@
+ retcode = 0;
+ } else {
+ /* Omit the four octet CRC from the length. */
+- nic->packetlen = rx_ring[entry].rxlength - 4;
+- memcpy(nic->packet, (char*)rx_ring[entry].bufaddr, nic->packetlen);
++ nic->packetlen = le32_to_cpu((rx_ring[entry].buflength))- 4;
++ memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen);
+ retcode = 1;
+ }
+
+@@ -395,17 +406,30 @@
+ rx_ring[entry].status = RRING_OWN;
+
+ /* Restart Receiver */
+- outl(CR_START_RX | CR_QUEUE_RX, command);
++ outl(CR_START_RX | CR_QUEUE_RX, command);
+
+ return retcode;
+ }
+
+
+ static void
+-epic100_disable(struct nic *nic)
++epic100_disable(struct dev *dev __unused)
+ {
++ /* Soft reset the chip. */
++ outl(GC_SOFT_RESET, genctl);
+ }
+
++static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
++{
++ switch ( action ) {
++ case DISABLE :
++ break;
++ case ENABLE :
++ break;
++ case FORCE :
++ break;
++ }
++}
+
+ #ifdef DEBUG_EEPROM
+ /* Serial EEPROM section. */
+@@ -479,3 +503,18 @@
+ break;
+ return inw(mmdata);
+ }
++
++
++static struct pci_id epic100_nics[] = {
++PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII"), /* SMC 83c170 EPIC/100 */
++PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175"),
++};
++
++struct pci_driver epic100_driver = {
++ .type = NIC_DRIVER,
++ .name = "EPIC100",
++ .probe = epic100_probe,
++ .ids = epic100_nics,
++ .id_count = sizeof(epic100_nics)/sizeof(epic100_nics[0]),
++ .class = 0,
++};
+diff -Naur grub-0.97.orig/netboot/etherboot.h grub-0.97/netboot/etherboot.h
+--- grub-0.97.orig/netboot/etherboot.h 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/etherboot.h 2005-08-31 19:03:35.000000000 +0000
+@@ -1,6 +1,6 @@
+ /*
+ * GRUB -- GRand Unified Bootloader
+- * Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
++ * Copyright (C) 1999,2000,2001,2002,2003,2004 Free Software Foundation, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+@@ -17,531 +17,45 @@
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+-/* RULE: You must define the macro ``GRUB'' when including this header
+- file in GRUB code. */
+-
+-/* Based on "src/etherboot.h" in etherboot-5.0.5. */
+-
+-/**************************************************************************
+-ETHERBOOT - BOOTP/TFTP Bootstrap Program
+-
+-Author: Martin Renters
+- Date: Dec/93
+-
+-**************************************************************************/
+-
+-/* Include GRUB-specific macros and prototypes here. */
+-#include <shared.h>
+-
+-/* FIXME: For now, enable the DHCP support. Perhaps I should segregate
+- the DHCP support from the BOOTP support, and permit both to
+- co-exist. */
+-#undef NO_DHCP_SUPPORT
+-
+-/* In GRUB, the relocated address in Etherboot doesn't have any sense.
+- Just define it as a bogus value. */
+-#define RELOC 0
+-
+-/* FIXME: Should be an option. */
+-#define BACKOFF_LIMIT 7
+-
+-#include <osdep.h>
+-
+-#define CTRL_C 3
+-
+-#ifndef MAX_TFTP_RETRIES
+-# define MAX_TFTP_RETRIES 20
+-#endif
+-
+-#ifndef MAX_BOOTP_RETRIES
+-# define MAX_BOOTP_RETRIES 20
+-#endif
+-
+-#define MAX_BOOTP_EXTLEN (ETH_FRAME_LEN - ETH_HLEN - \
+- sizeof (struct bootp_t))
++/*
++ * Transport layer to use Etherboot NIC drivers in GRUB.
++ */
+
+-#ifndef MAX_ARP_RETRIES
+-# define MAX_ARP_RETRIES 20
+-#endif
++#ifndef ETHERBOOT_H
++#define ETHERBOOT_H
+
+-#ifndef MAX_RPC_RETRIES
+-# define MAX_RPC_RETRIES 20
++#include "shared.h"
++#include "osdep.h"
++#include "if_ether.h"
++#include "in.h"
++
++/* Link configuration time in tenths of a second */
++#ifndef VALID_LINK_TIMEOUT
++#define VALID_LINK_TIMEOUT 100 /* 10.0 seconds */
+ #endif
+
+-#define TICKS_PER_SEC 18
+-
+-/* Inter-packet retry in ticks */
+-#define TIMEOUT (10 * TICKS_PER_SEC)
+-
+-/* These settings have sense only if compiled with -DCONGESTED */
+-/* total retransmission timeout in ticks */
+-#define TFTP_TIMEOUT (30 * TICKS_PER_SEC)
+-/* packet retransmission timeout in ticks */
+-#define TFTP_REXMT (3 * TICKS_PER_SEC)
+-
+ #ifndef NULL
+-# define NULL ((void *) 0)
++#define NULL ((void *)0)
+ #endif
+
+-/*
+- I'm moving towards the defined names in linux/if_ether.h for clarity.
+- The confusion between 60/64 and 1514/1518 arose because the NS8390
+- counts the 4 byte frame checksum in the incoming packet, but not
+- in the outgoing packet. 60/1514 are the correct numbers for most
+- if not all of the other NIC controllers. I will be retiring the
+- 64/1518 defines in the lead-up to 5.0.
+-*/
+-
+-#define ETH_ALEN 6 /* Size of Ethernet address */
+-#define ETH_HLEN 14 /* Size of ethernet header */
+-#define ETH_ZLEN 60 /* Minimum packet */
+-/*#define ETH_MIN_PACKET 64*/
+-#define ETH_FRAME_LEN 1514 /* Maximum packet */
+-/*#define ETH_MAX_PACKET 1518*/
+-/* Because some DHCP/BOOTP servers don't treat the maximum length the same
+- as Etherboot, subtract the size of an IP header and that of an UDP
+- header. */
+-#define ETH_MAX_MTU (ETH_FRAME_LEN - ETH_HLEN \
+- - sizeof (struct iphdr) \
+- - sizeof (struct udphdr))
+-
+-#define ARP_CLIENT 0
+-#define ARP_SERVER 1
+-#define ARP_GATEWAY 2
+-#define ARP_ROOTSERVER 3
+-#define ARP_SWAPSERVER 4
+-#define MAX_ARP ARP_SWAPSERVER+1
+-
+-#define RARP_REQUEST 3
+-#define RARP_REPLY 4
+-
+-#define IP 0x0800
+-#define ARP 0x0806
+-#define RARP 0x8035
+-
+-#define BOOTP_SERVER 67
+-#define BOOTP_CLIENT 68
+-#define TFTP_PORT 69
+-#define SUNRPC_PORT 111
+-
+-#define IP_UDP 17
+-/* Same after going through htonl */
+-#define IP_BROADCAST 0xFFFFFFFF
+-
+-#define ARP_REQUEST 1
+-#define ARP_REPLY 2
+-
+-#define BOOTP_REQUEST 1
+-#define BOOTP_REPLY 2
+-
+-#define TAG_LEN(p) (*((p) + 1))
+-#define RFC1533_COOKIE 99, 130, 83, 99
+-#define RFC1533_PAD 0
+-#define RFC1533_NETMASK 1
+-#define RFC1533_TIMEOFFSET 2
+-#define RFC1533_GATEWAY 3
+-#define RFC1533_TIMESERVER 4
+-#define RFC1533_IEN116NS 5
+-#define RFC1533_DNS 6
+-#define RFC1533_LOGSERVER 7
+-#define RFC1533_COOKIESERVER 8
+-#define RFC1533_LPRSERVER 9
+-#define RFC1533_IMPRESSSERVER 10
+-#define RFC1533_RESOURCESERVER 11
+-#define RFC1533_HOSTNAME 12
+-#define RFC1533_BOOTFILESIZE 13
+-#define RFC1533_MERITDUMPFILE 14
+-#define RFC1533_DOMAINNAME 15
+-#define RFC1533_SWAPSERVER 16
+-#define RFC1533_ROOTPATH 17
+-#define RFC1533_EXTENSIONPATH 18
+-#define RFC1533_IPFORWARDING 19
+-#define RFC1533_IPSOURCEROUTING 20
+-#define RFC1533_IPPOLICYFILTER 21
+-#define RFC1533_IPMAXREASSEMBLY 22
+-#define RFC1533_IPTTL 23
+-#define RFC1533_IPMTU 24
+-#define RFC1533_IPMTUPLATEAU 25
+-#define RFC1533_INTMTU 26
+-#define RFC1533_INTLOCALSUBNETS 27
+-#define RFC1533_INTBROADCAST 28
+-#define RFC1533_INTICMPDISCOVER 29
+-#define RFC1533_INTICMPRESPOND 30
+-#define RFC1533_INTROUTEDISCOVER 31
+-#define RFC1533_INTROUTESOLICIT 32
+-#define RFC1533_INTSTATICROUTES 33
+-#define RFC1533_LLTRAILERENCAP 34
+-#define RFC1533_LLARPCACHETMO 35
+-#define RFC1533_LLETHERNETENCAP 36
+-#define RFC1533_TCPTTL 37
+-#define RFC1533_TCPKEEPALIVETMO 38
+-#define RFC1533_TCPKEEPALIVEGB 39
+-#define RFC1533_NISDOMAIN 40
+-#define RFC1533_NISSERVER 41
+-#define RFC1533_NTPSERVER 42
+-#define RFC1533_VENDOR 43
+-#define RFC1533_NBNS 44
+-#define RFC1533_NBDD 45
+-#define RFC1533_NBNT 46
+-#define RFC1533_NBSCOPE 47
+-#define RFC1533_XFS 48
+-#define RFC1533_XDM 49
+-#ifndef NO_DHCP_SUPPORT
+-#define RFC2132_REQ_ADDR 50
+-#define RFC2132_MSG_TYPE 53
+-#define RFC2132_SRV_ID 54
+-#define RFC2132_PARAM_LIST 55
+-#define RFC2132_MAX_SIZE 57
+-#define RFC2132_VENDOR_CLASS_ID 60
+-
+-#define DHCPDISCOVER 1
+-#define DHCPOFFER 2
+-#define DHCPREQUEST 3
+-#define DHCPACK 5
+-#endif /* NO_DHCP_SUPPORT */
+-
+-#define RFC1533_VENDOR_MAJOR 0
+-#define RFC1533_VENDOR_MINOR 0
+-
+-#define RFC1533_VENDOR_MAGIC 128
+-#define RFC1533_VENDOR_ADDPARM 129
+-#define RFC1533_VENDOR_MNUOPTS 160
+-#define RFC1533_VENDOR_SELECTION 176
+-#define RFC1533_VENDOR_MOTD 184
+-#define RFC1533_VENDOR_NUMOFMOTD 8
+-#define RFC1533_VENDOR_IMG 192
+-#define RFC1533_VENDOR_NUMOFIMG 16
+-
+-#define RFC1533_VENDOR_CONFIGFILE 150
+-
+-#define RFC1533_END 255
+-
+-#define BOOTP_VENDOR_LEN 64
+-#ifndef NO_DHCP_SUPPORT
+-#define DHCP_OPT_LEN 312
+-#endif /* NO_DHCP_SUPPORT */
+-
+-#define TFTP_DEFAULTSIZE_PACKET 512
+-#define TFTP_MAX_PACKET 1432 /* 512 */
+-
+-#define TFTP_RRQ 1
+-#define TFTP_WRQ 2
+-#define TFTP_DATA 3
+-#define TFTP_ACK 4
+-#define TFTP_ERROR 5
+-#define TFTP_OACK 6
+-
+-#define TFTP_CODE_EOF 1
+-#define TFTP_CODE_MORE 2
+-#define TFTP_CODE_ERROR 3
+-#define TFTP_CODE_BOOT 4
+-#define TFTP_CODE_CFG 5
+-
+-#define AWAIT_ARP 0
+-#define AWAIT_BOOTP 1
+-#define AWAIT_TFTP 2
+-#define AWAIT_RARP 3
+-#define AWAIT_RPC 4
+-#define AWAIT_QDRAIN 5 /* drain queue, process ARP requests */
+-
+-typedef struct
+-{
+- unsigned long s_addr;
+-}
+-in_addr;
+-
+-struct arptable_t
+-{
+- in_addr ipaddr;
+- unsigned char node[6];
+-};
+-
+-/*
+- * A pity sipaddr and tipaddr are not longword aligned or we could use
+- * in_addr. No, I don't want to use #pragma packed.
+- */
+-struct arprequest
+-{
+- unsigned short hwtype;
+- unsigned short protocol;
+- char hwlen;
+- char protolen;
+- unsigned short opcode;
+- char shwaddr[6];
+- char sipaddr[4];
+- char thwaddr[6];
+- char tipaddr[4];
+-};
+-
+-struct iphdr
+-{
+- char verhdrlen;
+- char service;
+- unsigned short len;
+- unsigned short ident;
+- unsigned short frags;
+- char ttl;
+- char protocol;
+- unsigned short chksum;
+- in_addr src;
+- in_addr dest;
+-};
+-
+-struct udphdr
+-{
+- unsigned short src;
+- unsigned short dest;
+- unsigned short len;
+- unsigned short chksum;
+-};
+-
+-/* Format of a bootp packet. */
+-struct bootp_t
+-{
+- char bp_op;
+- char bp_htype;
+- char bp_hlen;
+- char bp_hops;
+- unsigned long bp_xid;
+- unsigned short bp_secs;
+- unsigned short unused;
+- in_addr bp_ciaddr;
+- in_addr bp_yiaddr;
+- in_addr bp_siaddr;
+- in_addr bp_giaddr;
+- char bp_hwaddr[16];
+- char bp_sname[64];
+- char bp_file[128];
+-#ifdef NO_DHCP_SUPPORT
+- char bp_vend[BOOTP_VENDOR_LEN];
+-#else
+- char bp_vend[DHCP_OPT_LEN];
+-#endif /* NO_DHCP_SUPPORT */
+-};
+-
+-/* Format of a bootp IP packet. */
+-struct bootpip_t
+-{
+- struct iphdr ip;
+- struct udphdr udp;
+- struct bootp_t bp;
+-};
+-
+-/* Format of bootp packet with extensions. */
+-struct bootpd_t
+-{
+- struct bootp_t bootp_reply;
+- unsigned char bootp_extension[MAX_BOOTP_EXTLEN];
+-};
+-
+-struct tftp_t
+-{
+- struct iphdr ip;
+- struct udphdr udp;
+- unsigned short opcode;
+- union
+- {
+- char rrq[TFTP_DEFAULTSIZE_PACKET];
+-
+- struct
+- {
+- unsigned short block;
+- char download[TFTP_MAX_PACKET];
+- }
+- data;
+-
+- struct
+- {
+- unsigned short block;
+- }
+- ack;
+-
+- struct
+- {
+- unsigned short errcode;
+- char errmsg[TFTP_DEFAULTSIZE_PACKET];
+- }
+- err;
+-
+- struct
+- {
+- char data[TFTP_DEFAULTSIZE_PACKET+2];
+- }
+- oack;
+- }
+- u;
+-};
+-
+-/* Define a smaller tftp packet solely for making requests to conserve stack
+- 512 bytes should be enough. */
+-struct tftpreq_t
+-{
+- struct iphdr ip;
+- struct udphdr udp;
+- unsigned short opcode;
+- union
+- {
+- char rrq[512];
+-
+- struct
+- {
+- unsigned short block;
+- }
+- ack;
+-
+- struct
+- {
+- unsigned short errcode;
+- char errmsg[512-2];
+- }
+- err;
+- }
+- u;
+-};
+-
+-#define TFTP_MIN_PACKET (sizeof(struct iphdr) + sizeof(struct udphdr) + 4)
+-
+-struct rpc_t
+-{
+- struct iphdr ip;
+- struct udphdr udp;
+- union
+- {
+- char data[300]; /* longest RPC call must fit!!!! */
+-
+- struct
+- {
+- long id;
+- long type;
+- long rpcvers;
+- long prog;
+- long vers;
+- long proc;
+- long data[1];
+- }
+- call;
+-
+- struct
+- {
+- long id;
+- long type;
+- long rstatus;
+- long verifier;
+- long v2;
+- long astatus;
+- long data[1];
+- }
+- reply;
+- }
+- u;
+-};
+-
+-#define PROG_PORTMAP 100000
+-#define PROG_NFS 100003
+-#define PROG_MOUNT 100005
+-
+-#define MSG_CALL 0
+-#define MSG_REPLY 1
+-
+-#define PORTMAP_GETPORT 3
+-
+-#define MOUNT_ADDENTRY 1
+-#define MOUNT_UMOUNTALL 4
+-
+-#define NFS_LOOKUP 4
+-#define NFS_READ 6
+-
+-#define NFS_FHSIZE 32
+-
+-#define NFSERR_PERM 1
+-#define NFSERR_NOENT 2
+-#define NFSERR_ACCES 13
+-
+-/* Block size used for NFS read accesses. A RPC reply packet (including all
+- * headers) must fit within a single Ethernet frame to avoid fragmentation.
+- * Chosen to be a power of two, as most NFS servers are optimized for this. */
+-#define NFS_READ_SIZE 1024
+-
+-#define FLOPPY_BOOT_LOCATION 0x7c00
+-/* Must match offsets in loader.S */
+-#define ROM_SEGMENT 0x1fa
+-#define ROM_LENGTH 0x1fc
+-
+-#define ROM_INFO_LOCATION (FLOPPY_BOOT_LOCATION + ROM_SEGMENT)
+-/* at end of floppy boot block */
+-
+-struct rom_info
+-{
+- unsigned short rom_segment;
+- unsigned short rom_length;
+-};
+-
+-static inline int
+-rom_address_ok (struct rom_info *rom, int assigned_rom_segment)
+-{
+- return (assigned_rom_segment < 0xC000
+- || assigned_rom_segment == rom->rom_segment);
+-}
+-
+-/* Define a type for passing info to a loaded program. */
+-struct ebinfo
+-{
+- unsigned char major, minor; /* Version */
+- unsigned short flags; /* Bit flags */
+-};
+-
+-/***************************************************************************
+-External prototypes
+-***************************************************************************/
+-/* main.c */
+-extern void print_network_configuration (void);
+-extern int ifconfig (char *ip, char *sm, char *gw, char *svr);
+-extern int udp_transmit (unsigned long destip, unsigned int srcsock,
+- unsigned int destsock, int len, const void *buf);
+-extern int await_reply (int type, int ival, void *ptr, int timeout);
+-extern int decode_rfc1533 (unsigned char *, int, int, int);
+-extern long rfc2131_sleep_interval (int base, int exp);
+-extern void cleanup (void);
+-extern int rarp (void);
+-extern int bootp (void);
+-extern void cleanup_net (void);
+-
+-/* config.c */
+-extern void print_config (void);
+-extern void eth_reset (void);
+-extern int eth_probe (void);
+-extern int eth_poll (void);
+-extern void eth_transmit (const char *d, unsigned int t,
+- unsigned int s, const void *p);
+-extern void eth_disable (void);
+-
+-/* misc.c */
+-extern void twiddle (void);
+-extern void sleep (int secs);
+-extern int getdec (char **s);
+-extern void etherboot_printf (const char *, ...);
+-extern int etherboot_sprintf (char *, const char *, ...);
+-extern int inet_aton (char *p, in_addr *i);
+-
+-/***************************************************************************
+-External variables
+-***************************************************************************/
+-/* main.c */
+-extern int ip_abort;
+-extern int network_ready;
+-extern struct rom_info rom;
+-extern struct arptable_t arptable[MAX_ARP];
+-extern struct bootpd_t bootp_data;
+-#define BOOTP_DATA_ADDR (&bootp_data)
+-extern unsigned char *end_of_rfc1533;
+
+-/* config.c */
+-extern struct nic nic;
++#define gateA20_set() gateA20(1)
++#define gateA20_unset() gateA20(0)
++#define EBDEBUG 0
++/* The 'rom_info' maybe arch depended. It must be moved to some other
++ * place */
++struct rom_info {
++ unsigned short rom_segment;
++ unsigned short rom_length;
++};
++
++extern void poll_interruptions P((void));
++
++/* For UNDI drivers */
++extern void fake_irq ( uint8_t irq );
++extern void _trivial_irq_handler_start;
++extern uint32_t get_free_base_memory ( void );
++extern void forget_base_memory ( void*, size_t );
++extern void free_unused_base_memory ( void );
+
+-/* Local hack - define some macros to use etherboot source files "as is". */
+-#ifndef GRUB
+-# undef printf
+-# define printf etherboot_printf
+-# undef sprintf
+-# define sprintf etherboot_sprintf
+-#endif /* GRUB */
++#endif /* ETHERBOOT_H */
+diff -Naur grub-0.97.orig/netboot/fa311.c grub-0.97/netboot/fa311.c
+--- grub-0.97.orig/netboot/fa311.c 2003-07-09 11:45:37.000000000 +0000
++++ grub-0.97/netboot/fa311.c 1970-01-01 00:00:00.000000000 +0000
+@@ -1,421 +0,0 @@
+-/*
+- Driver for the National Semiconductor DP83810 Ethernet controller.
+-
+- Portions Copyright (C) 2001 Inprimis Technologies, Inc.
+- http://www.inprimis.com/
+-
+- This driver is based (heavily) on the Linux driver for this chip
+- which is copyright 1999-2001 by Donald Becker.
+-
+- This software has no warranties expressed or implied for any
+- purpose.
+-
+- This software may be used and distributed according to the terms of
+- the GNU General Public License (GPL), incorporated herein by reference.
+- Drivers based on or derived from this code fall under the GPL and must
+- retain the authorship, copyright and license notice. This file is not
+- a complete program and may only be used when the entire operating
+- system is licensed under the GPL. License for under other terms may be
+- available. Contact the original author for details.
+-
+- The original author may be reached as becker@scyld.com, or at
+- Scyld Computing Corporation
+- 410 Severn Ave., Suite 210
+- Annapolis MD 21403
+-*/
+-
+-
+-typedef unsigned char u8;
+-typedef signed char s8;
+-typedef unsigned short u16;
+-typedef signed short s16;
+-typedef unsigned int u32;
+-typedef signed int s32;
+-
+-#include "etherboot.h"
+-#include "nic.h"
+-#include "pci.h"
+-
+-#undef virt_to_bus
+-#define virt_to_bus(x) ((unsigned long)x)
+-#define cpu_to_le32(val) (val)
+-#define le32_to_cpu(val) (val)
+-#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
+-#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
+-
+-#define TX_RING_SIZE 1
+-#define RX_RING_SIZE 4
+-#define TIME_OUT 1000000
+-#define PKT_BUF_SZ 1536
+-
+-/* Offsets to the device registers. */
+-enum register_offsets {
+- ChipCmd=0x00, ChipConfig=0x04, EECtrl=0x08, PCIBusCfg=0x0C,
+- IntrStatus=0x10, IntrMask=0x14, IntrEnable=0x18,
+- TxRingPtr=0x20, TxConfig=0x24,
+- RxRingPtr=0x30, RxConfig=0x34,
+- WOLCmd=0x40, PauseCmd=0x44, RxFilterAddr=0x48, RxFilterData=0x4C,
+- BootRomAddr=0x50, BootRomData=0x54, StatsCtrl=0x5C, StatsData=0x60,
+- RxPktErrs=0x60, RxMissed=0x68, RxCRCErrs=0x64,
+-};
+-
+-/* Bit in ChipCmd. */
+-enum ChipCmdBits {
+- ChipReset=0x100, RxReset=0x20, TxReset=0x10, RxOff=0x08, RxOn=0x04,
+- TxOff=0x02, TxOn=0x01,
+-};
+-
+-/* Bits in the interrupt status/mask registers. */
+-enum intr_status_bits {
+- IntrRxDone=0x0001, IntrRxIntr=0x0002, IntrRxErr=0x0004, IntrRxEarly=0x0008,
+- IntrRxIdle=0x0010, IntrRxOverrun=0x0020,
+- IntrTxDone=0x0040, IntrTxIntr=0x0080, IntrTxErr=0x0100,
+- IntrTxIdle=0x0200, IntrTxUnderrun=0x0400,
+- StatsMax=0x0800, LinkChange=0x4000, WOLPkt=0x2000,
+- RxResetDone=0x1000000, TxResetDone=0x2000000,
+- IntrPCIErr=0x00f00000, IntrNormalSummary=0x0251, IntrAbnormalSummary=0xED20,
+-};
+-
+-/* Bits in the RxMode register. */
+-enum rx_mode_bits {
+- AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0xC0000000,
+- AcceptMulticast=0x00200000, AcceptAllMulticast=0x20000000,
+- AcceptAllPhys=0x10000000, AcceptMyPhys=0x08000000,
+-};
+-
+-/* Bits in network_desc.status */
+-enum desc_status_bits {
+- DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
+- DescNoCRC=0x10000000,
+- DescPktOK=0x08000000, RxTooLong=0x00400000,
+-};
+-
+-/* The Rx and Tx buffer descriptors. */
+-struct netdev_desc {
+- u32 next_desc;
+- s32 cmd_status;
+- u32 addr;
+-};
+-
+-static struct FA311_DEV {
+- unsigned int ioaddr;
+- unsigned short vendor;
+- unsigned short device;
+- unsigned int cur_rx;
+- unsigned int cur_tx;
+- unsigned int rx_buf_sz;
+- volatile struct netdev_desc *rx_head_desc;
+- volatile struct netdev_desc rx_ring[RX_RING_SIZE] __attribute__ ((aligned (4)));
+- volatile struct netdev_desc tx_ring[TX_RING_SIZE] __attribute__ ((aligned (4)));
+-} fa311_dev;
+-
+-static int eeprom_read(long ioaddr, int location);
+-static void init_ring(struct FA311_DEV *dev);
+-static void fa311_reset(struct nic *nic);
+-static int fa311_poll(struct nic *nic);
+-static void fa311_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p);
+-static void fa311_disable(struct nic *nic);
+-
+-static char rx_packet[PKT_BUF_SZ * RX_RING_SIZE] __attribute__ ((aligned (4)));
+-static char tx_packet[PKT_BUF_SZ * TX_RING_SIZE] __attribute__ ((aligned (4)));
+-
+-struct nic * fa311_probe(struct nic *nic, unsigned short *io_addrs, struct pci_device *pci)
+-{
+-int prev_eedata;
+-int i;
+-int duplex;
+-int tx_config;
+-int rx_config;
+-unsigned char macaddr[6];
+-unsigned char mactest;
+-unsigned char pci_bus = 0;
+-struct FA311_DEV* dev = &fa311_dev;
+-
+- if (io_addrs == 0 || *io_addrs == 0)
+- return (0);
+- memset(dev, 0, sizeof(*dev));
+- dev->vendor = pci->vendor;
+- dev->device = pci->dev_id;
+- dev->ioaddr = pci->membase;
+-
+- /* Work around the dropped serial bit. */
+- prev_eedata = eeprom_read(dev->ioaddr, 6);
+- for (i = 0; i < 3; i++) {
+- int eedata = eeprom_read(dev->ioaddr, i + 7);
+- macaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
+- macaddr[i*2+1] = eedata >> 7;
+- prev_eedata = eedata;
+- }
+- mactest = 0;
+- for (i = 0; i < 6; i++)
+- mactest |= macaddr[i];
+- if (mactest == 0)
+- return (0);
+- for (i = 0; i < 6; i++)
+- nic->node_addr[i] = macaddr[i];
+- printf("%! ", nic->node_addr);
+-
+- adjust_pci_device(pci);
+-
+- fa311_reset(nic);
+-
+- nic->reset = fa311_reset;
+- nic->disable = fa311_disable;
+- nic->poll = fa311_poll;
+- nic->transmit = fa311_transmit;
+-
+- init_ring(dev);
+-
+- writel(virt_to_bus(dev->rx_ring), dev->ioaddr + RxRingPtr);
+- writel(virt_to_bus(dev->tx_ring), dev->ioaddr + TxRingPtr);
+-
+- for (i = 0; i < 6; i += 2)
+- {
+- writel(i, dev->ioaddr + RxFilterAddr);
+- writew(macaddr[i] + (macaddr[i+1] << 8),
+- dev->ioaddr + RxFilterData);
+- }
+-
+- /* Initialize other registers. */
+- /* Configure for standard, in-spec Ethernet. */
+- if (readl(dev->ioaddr + ChipConfig) & 0x20000000)
+- { /* Full duplex */
+- tx_config = 0xD0801002;
+- rx_config = 0x10000020;
+- }
+- else
+- {
+- tx_config = 0x10801002;
+- rx_config = 0x0020;
+- }
+- writel(tx_config, dev->ioaddr + TxConfig);
+- writel(rx_config, dev->ioaddr + RxConfig);
+-
+- duplex = readl(dev->ioaddr + ChipConfig) & 0x20000000 ? 1 : 0;
+- if (duplex) {
+- rx_config |= 0x10000000;
+- tx_config |= 0xC0000000;
+- } else {
+- rx_config &= ~0x10000000;
+- tx_config &= ~0xC0000000;
+- }
+- writew(tx_config, dev->ioaddr + TxConfig);
+- writew(rx_config, dev->ioaddr + RxConfig);
+-
+- writel(AcceptBroadcast | AcceptAllMulticast | AcceptMyPhys,
+- dev->ioaddr + RxFilterAddr);
+-
+- writel(RxOn | TxOn, dev->ioaddr + ChipCmd);
+- writel(4, dev->ioaddr + StatsCtrl); /* Clear Stats */
+- return nic;
+-
+-}
+-
+-static void fa311_reset(struct nic *nic)
+-{
+-u32 chip_config;
+-struct FA311_DEV* dev = &fa311_dev;
+-
+- /* Reset the chip to erase previous misconfiguration. */
+- outl(ChipReset, dev->ioaddr + ChipCmd);
+-
+- if ((readl(dev->ioaddr + ChipConfig) & 0xe000) != 0xe000)
+- {
+- chip_config = readl(dev->ioaddr + ChipConfig);
+- }
+-}
+-
+-static int fa311_poll(struct nic *nic)
+-{
+-s32 desc_status;
+-int to;
+-int entry;
+-int retcode;
+-struct FA311_DEV* dev = &fa311_dev;
+-
+- retcode = 0;
+- entry = dev->cur_rx;
+- to = TIME_OUT;
+- while (to != 0)
+- {
+- desc_status = dev->rx_ring[entry].cmd_status;
+- if ((desc_status & DescOwn) != 0)
+- break;
+- else
+- --to;
+- }
+- if (to != 0)
+- {
+- readl(dev->ioaddr + IntrStatus); /* clear interrrupt bits */
+- /* driver owns the next entry it's a new packet. Send it up. */
+- if ((desc_status & (DescMore|DescPktOK|RxTooLong)) == DescPktOK)
+- {
+- nic->packetlen = (desc_status & 0x0fff) - 4; /* Omit CRC size. */
+- memcpy(nic->packet, (char*)(dev->rx_ring[entry].addr), nic->packetlen);
+- retcode = 1;
+- }
+- /* Give the descriptor back to the chip */
+- dev->rx_ring[entry].cmd_status = cpu_to_le32(dev->rx_buf_sz);
+- dev->cur_rx++;
+- if (dev->cur_rx >= RX_RING_SIZE)
+- dev->cur_rx = 0;
+- dev->rx_head_desc = &dev->rx_ring[dev->cur_rx];
+- }
+- /* Restart Rx engine if stopped. */
+- writel(RxOn, dev->ioaddr + ChipCmd);
+- return retcode;
+-}
+-
+-static void fa311_transmit(struct nic *nic, const char *destaddr, unsigned int type, unsigned int len, const char *data)
+-{
+-unsigned short nstype;
+-s32 desc_status;
+-int to;
+-int entry;
+-char* txp;
+-unsigned char* s;
+-struct FA311_DEV* dev = &fa311_dev;
+-
+- /* Calculate the next Tx descriptor entry. */
+- entry = dev->cur_tx;
+- txp = (char*)(dev->tx_ring[entry].addr);
+-
+- memcpy(txp, destaddr, ETH_ALEN);
+- memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
+- nstype = htons(type);
+- memcpy(txp + 12, (char*)&nstype, 2);
+- memcpy(txp + ETH_HLEN, data, len);
+- len += ETH_HLEN;
+- /* pad frame */
+- if (len < ETH_ZLEN)
+- {
+- s = (unsigned char*)(txp+len);
+- while (s < (unsigned char*)(txp+ETH_ZLEN))
+- *s++ = 0;
+- len = ETH_ZLEN;
+- }
+- dev->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | len);
+- dev->cur_tx++;
+- if (dev->cur_tx >= TX_RING_SIZE)
+- dev->cur_tx = 0;
+-
+- /* Wake the potentially-idle transmit channel. */
+- writel(TxOn, dev->ioaddr + ChipCmd);
+-
+- /* wait for tranmission to complete */
+- to = TIME_OUT;
+- while (to != 0)
+- {
+- desc_status = dev->tx_ring[entry].cmd_status;
+- if ((desc_status & DescOwn) == 0)
+- break;
+- else
+- --to;
+- }
+-
+- readl(dev->ioaddr + IntrStatus); /* clear interrrupt bits */
+- return;
+-}
+-
+-static void fa311_disable(struct nic *nic)
+-{
+-struct FA311_DEV* dev = &fa311_dev;
+-
+- /* Stop the chip's Tx and Rx processes. */
+- writel(RxOff | TxOff, dev->ioaddr + ChipCmd);
+-}
+-
+-
+-/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
+- The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
+-
+-/* Delay between EEPROM clock transitions.
+- No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
+- a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
+- made udelay() unreliable.
+- The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
+- depricated.
+-*/
+-#define eeprom_delay(ee_addr) inl(ee_addr)
+-
+-enum EEPROM_Ctrl_Bits {
+- EE_ShiftClk=0x04, EE_DataIn=0x01, EE_ChipSelect=0x08, EE_DataOut=0x02,
+-};
+-#define EE_Write0 (EE_ChipSelect)
+-#define EE_Write1 (EE_ChipSelect | EE_DataIn)
+-
+-/* The EEPROM commands include the alway-set leading bit. */
+-enum EEPROM_Cmds {
+- EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
+-};
+-
+-
+-static int eeprom_read(long addr, int location)
+-{
+- int i;
+- int retval = 0;
+- int ee_addr = addr + EECtrl;
+- int read_cmd = location | EE_ReadCmd;
+- writel(EE_Write0, ee_addr);
+-
+- /* Shift the read command bits out. */
+- for (i = 10; i >= 0; i--) {
+- short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
+- writel(dataval, ee_addr);
+- eeprom_delay(ee_addr);
+- writel(dataval | EE_ShiftClk, ee_addr);
+- eeprom_delay(ee_addr);
+- }
+- writel(EE_ChipSelect, ee_addr);
+- eeprom_delay(ee_addr);
+-
+- for (i = 0; i < 16; i++) {
+- writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
+- eeprom_delay(ee_addr);
+- retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
+- writel(EE_ChipSelect, ee_addr);
+- eeprom_delay(ee_addr);
+- }
+-
+- /* Terminate the EEPROM access. */
+- writel(EE_Write0, ee_addr);
+- writel(0, ee_addr);
+- return retval;
+-}
+-
+-/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
+-static void init_ring(struct FA311_DEV *dev)
+-{
+- int i;
+-
+- dev->cur_rx = 0;
+- dev->cur_tx = 0;
+-
+- dev->rx_buf_sz = PKT_BUF_SZ;
+- dev->rx_head_desc = &dev->rx_ring[0];
+-
+- /* Initialize all Rx descriptors. */
+- for (i = 0; i < RX_RING_SIZE; i++) {
+- dev->rx_ring[i].next_desc = virt_to_le32desc(&dev->rx_ring[i+1]);
+- dev->rx_ring[i].cmd_status = DescOwn;
+- }
+- /* Mark the last entry as wrapping the ring. */
+- dev->rx_ring[i-1].next_desc = virt_to_le32desc(&dev->rx_ring[0]);
+-
+- /* Fill in the Rx buffers. Handle allocation failure gracefully. */
+- for (i = 0; i < RX_RING_SIZE; i++) {
+- dev->rx_ring[i].addr = (u32)(&rx_packet[PKT_BUF_SZ * i]);
+- dev->rx_ring[i].cmd_status = cpu_to_le32(dev->rx_buf_sz);
+- }
+-
+- for (i = 0; i < TX_RING_SIZE; i++) {
+- dev->tx_ring[i].next_desc = virt_to_le32desc(&dev->tx_ring[i+1]);
+- dev->tx_ring[i].cmd_status = 0;
+- }
+- dev->tx_ring[i-1].next_desc = virt_to_le32desc(&dev->tx_ring[0]);
+-
+- for (i = 0; i < TX_RING_SIZE; i++)
+- dev->tx_ring[i].addr = (u32)(&tx_packet[PKT_BUF_SZ * i]);
+- return;
+-}
+-
+diff -Naur grub-0.97.orig/netboot/forcedeth.c grub-0.97/netboot/forcedeth.c
+--- grub-0.97.orig/netboot/forcedeth.c 1970-01-01 00:00:00.000000000 +0000
++++ grub-0.97/netboot/forcedeth.c 2005-08-31 19:03:35.000000000 +0000
+@@ -0,0 +1,1039 @@
++/**************************************************************************
++* forcedeth.c -- Etherboot device driver for the NVIDIA nForce
++* media access controllers.
++*
++* Note: This driver is based on the Linux driver that was based on
++* a cleanroom reimplementation which was based on reverse
++* engineered documentation written by Carl-Daniel Hailfinger
++* and Andrew de Quincey. It's neither supported nor endorsed
++* by NVIDIA Corp. Use at your own risk.
++*
++* Written 2004 by Timothy Legge <tlegge@rogers.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the License, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not, write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++* Portions of this code based on:
++* forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
++*
++* (C) 2003 Manfred Spraul
++* See Linux Driver for full information
++*
++* Linux Driver Version 0.22, 19 Jan 2004
++*
++*
++* REVISION HISTORY:
++* ================
++* v1.0 01-31-2004 timlegge Initial port of Linux driver
++* v1.1 02-03-2004 timlegge Large Clean up, first release
++*
++* Indent Options: indent -kr -i8
++***************************************************************************/
++
++/* to get some global routines like printf */
++#include "etherboot.h"
++/* to get the interface to the body of the program */
++#include "nic.h"
++/* to get the PCI support functions, if this is a PCI NIC */
++#include "pci.h"
++/* Include timer support functions */
++#include "timer.h"
++
++#define drv_version "v1.1"
++#define drv_date "02-03-2004"
++
++//#define TFTM_DEBUG
++#ifdef TFTM_DEBUG
++#define dprintf(x) printf x
++#else
++#define dprintf(x)
++#endif
++
++typedef unsigned char u8;
++typedef signed char s8;
++typedef unsigned short u16;
++typedef signed short s16;
++typedef unsigned int u32;
++typedef signed int s32;
++
++/* Condensed operations for readability. */
++#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
++#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
++
++unsigned long BASE;
++/* NIC specific static variables go here */
++
++
++/*
++ * Hardware access:
++ */
++
++#define DEV_NEED_LASTPACKET1 0x0001
++#define DEV_IRQMASK_1 0x0002
++#define DEV_IRQMASK_2 0x0004
++#define DEV_NEED_TIMERIRQ 0x0008
++
++enum {
++ NvRegIrqStatus = 0x000,
++#define NVREG_IRQSTAT_MIIEVENT 0040
++#define NVREG_IRQSTAT_MASK 0x1ff
++ NvRegIrqMask = 0x004,
++#define NVREG_IRQ_RX 0x0002
++#define NVREG_IRQ_RX_NOBUF 0x0004
++#define NVREG_IRQ_TX_ERR 0x0008
++#define NVREG_IRQ_TX2 0x0010
++#define NVREG_IRQ_TIMER 0x0020
++#define NVREG_IRQ_LINK 0x0040
++#define NVREG_IRQ_TX1 0x0100
++#define NVREG_IRQMASK_WANTED_1 0x005f
++#define NVREG_IRQMASK_WANTED_2 0x0147
++#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
++
++ NvRegUnknownSetupReg6 = 0x008,
++#define NVREG_UNKSETUP6_VAL 3
++
++/*
++ * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
++ * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
++ */
++ NvRegPollingInterval = 0x00c,
++#define NVREG_POLL_DEFAULT 970
++ NvRegMisc1 = 0x080,
++#define NVREG_MISC1_HD 0x02
++#define NVREG_MISC1_FORCE 0x3b0f3c
++
++ NvRegTransmitterControl = 0x084,
++#define NVREG_XMITCTL_START 0x01
++ NvRegTransmitterStatus = 0x088,
++#define NVREG_XMITSTAT_BUSY 0x01
++
++ NvRegPacketFilterFlags = 0x8c,
++#define NVREG_PFF_ALWAYS 0x7F0008
++#define NVREG_PFF_PROMISC 0x80
++#define NVREG_PFF_MYADDR 0x20
++
++ NvRegOffloadConfig = 0x90,
++#define NVREG_OFFLOAD_HOMEPHY 0x601
++#define NVREG_OFFLOAD_NORMAL 0x5ee
++ NvRegReceiverControl = 0x094,
++#define NVREG_RCVCTL_START 0x01
++ NvRegReceiverStatus = 0x98,
++#define NVREG_RCVSTAT_BUSY 0x01
++
++ NvRegRandomSeed = 0x9c,
++#define NVREG_RNDSEED_MASK 0x00ff
++#define NVREG_RNDSEED_FORCE 0x7f00
++
++ NvRegUnknownSetupReg1 = 0xA0,
++#define NVREG_UNKSETUP1_VAL 0x16070f
++ NvRegUnknownSetupReg2 = 0xA4,
++#define NVREG_UNKSETUP2_VAL 0x16
++ NvRegMacAddrA = 0xA8,
++ NvRegMacAddrB = 0xAC,
++ NvRegMulticastAddrA = 0xB0,
++#define NVREG_MCASTADDRA_FORCE 0x01
++ NvRegMulticastAddrB = 0xB4,
++ NvRegMulticastMaskA = 0xB8,
++ NvRegMulticastMaskB = 0xBC,
++
++ NvRegTxRingPhysAddr = 0x100,
++ NvRegRxRingPhysAddr = 0x104,
++ NvRegRingSizes = 0x108,
++#define NVREG_RINGSZ_TXSHIFT 0
++#define NVREG_RINGSZ_RXSHIFT 16
++ NvRegUnknownTransmitterReg = 0x10c,
++ NvRegLinkSpeed = 0x110,
++#define NVREG_LINKSPEED_FORCE 0x10000
++#define NVREG_LINKSPEED_10 10
++#define NVREG_LINKSPEED_100 100
++#define NVREG_LINKSPEED_1000 1000
++ NvRegUnknownSetupReg5 = 0x130,
++#define NVREG_UNKSETUP5_BIT31 (1<<31)
++ NvRegUnknownSetupReg3 = 0x134,
++#define NVREG_UNKSETUP3_VAL1 0x200010
++ NvRegTxRxControl = 0x144,
++#define NVREG_TXRXCTL_KICK 0x0001
++#define NVREG_TXRXCTL_BIT1 0x0002
++#define NVREG_TXRXCTL_BIT2 0x0004
++#define NVREG_TXRXCTL_IDLE 0x0008
++#define NVREG_TXRXCTL_RESET 0x0010
++ NvRegMIIStatus = 0x180,
++#define NVREG_MIISTAT_ERROR 0x0001
++#define NVREG_MIISTAT_LINKCHANGE 0x0008
++#define NVREG_MIISTAT_MASK 0x000f
++#define NVREG_MIISTAT_MASK2 0x000f
++ NvRegUnknownSetupReg4 = 0x184,
++#define NVREG_UNKSETUP4_VAL 8
++
++ NvRegAdapterControl = 0x188,
++#define NVREG_ADAPTCTL_START 0x02
++#define NVREG_ADAPTCTL_LINKUP 0x04
++#define NVREG_ADAPTCTL_PHYVALID 0x4000
++#define NVREG_ADAPTCTL_RUNNING 0x100000
++#define NVREG_ADAPTCTL_PHYSHIFT 24
++ NvRegMIISpeed = 0x18c,
++#define NVREG_MIISPEED_BIT8 (1<<8)
++#define NVREG_MIIDELAY 5
++ NvRegMIIControl = 0x190,
++#define NVREG_MIICTL_INUSE 0x10000
++#define NVREG_MIICTL_WRITE 0x08000
++#define NVREG_MIICTL_ADDRSHIFT 5
++ NvRegMIIData = 0x194,
++ NvRegWakeUpFlags = 0x200,
++#define NVREG_WAKEUPFLAGS_VAL 0x7770
++#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
++#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
++#define NVREG_WAKEUPFLAGS_D3SHIFT 12
++#define NVREG_WAKEUPFLAGS_D2SHIFT 8
++#define NVREG_WAKEUPFLAGS_D1SHIFT 4
++#define NVREG_WAKEUPFLAGS_D0SHIFT 0
++#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
++#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
++#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
++
++ NvRegPatternCRC = 0x204,
++ NvRegPatternMask = 0x208,
++ NvRegPowerCap = 0x268,
++#define NVREG_POWERCAP_D3SUPP (1<<30)
++#define NVREG_POWERCAP_D2SUPP (1<<26)
++#define NVREG_POWERCAP_D1SUPP (1<<25)
++ NvRegPowerState = 0x26c,
++#define NVREG_POWERSTATE_POWEREDUP 0x8000
++#define NVREG_POWERSTATE_VALID 0x0100
++#define NVREG_POWERSTATE_MASK 0x0003
++#define NVREG_POWERSTATE_D0 0x0000
++#define NVREG_POWERSTATE_D1 0x0001
++#define NVREG_POWERSTATE_D2 0x0002
++#define NVREG_POWERSTATE_D3 0x0003
++};
++
++
++
++#define NV_TX_LASTPACKET (1<<0)
++#define NV_TX_RETRYERROR (1<<3)
++#define NV_TX_LASTPACKET1 (1<<8)
++#define NV_TX_DEFERRED (1<<10)
++#define NV_TX_CARRIERLOST (1<<11)
++#define NV_TX_LATECOLLISION (1<<12)
++#define NV_TX_UNDERFLOW (1<<13)
++#define NV_TX_ERROR (1<<14)
++#define NV_TX_VALID (1<<15)
++
++#define NV_RX_DESCRIPTORVALID (1<<0)
++#define NV_RX_MISSEDFRAME (1<<1)
++#define NV_RX_SUBSTRACT1 (1<<3)
++#define NV_RX_ERROR1 (1<<7)
++#define NV_RX_ERROR2 (1<<8)
++#define NV_RX_ERROR3 (1<<9)
++#define NV_RX_ERROR4 (1<<10)
++#define NV_RX_CRCERR (1<<11)
++#define NV_RX_OVERFLOW (1<<12)
++#define NV_RX_FRAMINGERR (1<<13)
++#define NV_RX_ERROR (1<<14)
++#define NV_RX_AVAIL (1<<15)
++
++/* Miscelaneous hardware related defines: */
++#define NV_PCI_REGSZ 0x270
++
++/* various timeout delays: all in usec */
++#define NV_TXRX_RESET_DELAY 4
++#define NV_TXSTOP_DELAY1 10
++#define NV_TXSTOP_DELAY1MAX 500000
++#define NV_TXSTOP_DELAY2 100
++#define NV_RXSTOP_DELAY1 10
++#define NV_RXSTOP_DELAY1MAX 500000
++#define NV_RXSTOP_DELAY2 100
++#define NV_SETUP5_DELAY 5
++#define NV_SETUP5_DELAYMAX 50000
++#define NV_POWERUP_DELAY 5
++#define NV_POWERUP_DELAYMAX 5000
++#define NV_MIIBUSY_DELAY 50
++#define NV_MIIPHY_DELAY 10
++#define NV_MIIPHY_DELAYMAX 10000
++
++#define NV_WAKEUPPATTERNS 5
++#define NV_WAKEUPMASKENTRIES 4
++
++/* General driver defaults */
++#define NV_WATCHDOG_TIMEO (2*HZ)
++#define DEFAULT_MTU 1500 /* also maximum supported, at least for now */
++
++#define RX_RING 4
++#define TX_RING 2
++/* limited to 1 packet until we understand NV_TX_LASTPACKET */
++#define TX_LIMIT_STOP 10
++#define TX_LIMIT_START 5
++
++/* rx/tx mac addr + type + vlan + align + slack*/
++#define RX_NIC_BUFSIZE (DEFAULT_MTU + 64)
++/* even more slack */
++#define RX_ALLOC_BUFSIZE (DEFAULT_MTU + 128)
++
++#define OOM_REFILL (1+HZ/20)
++#define POLL_WAIT (1+HZ/100)
++
++struct ring_desc {
++ u32 PacketBuffer;
++ u16 Length;
++ u16 Flags;
++};
++
++
++/* Define the TX Descriptor */
++static struct ring_desc tx_ring[TX_RING];
++
++/* Create a static buffer of size RX_BUF_SZ for each
++TX Descriptor. All descriptors point to a
++part of this buffer */
++static unsigned char txb[TX_RING * RX_NIC_BUFSIZE];
++
++/* Define the TX Descriptor */
++static struct ring_desc rx_ring[RX_RING];
++
++/* Create a static buffer of size RX_BUF_SZ for each
++RX Descriptor All descriptors point to a
++part of this buffer */
++static unsigned char rxb[RX_RING * RX_NIC_BUFSIZE];
++
++/* Private Storage for the NIC */
++struct forcedeth_private {
++ /* General data:
++ * Locking: spin_lock(&np->lock); */
++ int in_shutdown;
++ u32 linkspeed;
++ int duplex;
++ int phyaddr;
++
++ /* General data: RO fields */
++ u8 *ring_addr;
++ u32 orig_mac[2];
++ u32 irqmask;
++ /* rx specific fields.
++ * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
++ */
++ struct ring_desc *rx_ring;
++ unsigned int cur_rx, refill_rx;
++ struct sk_buff *rx_skbuff[RX_RING];
++ u32 rx_dma[RX_RING];
++ unsigned int rx_buf_sz;
++
++ /*
++ * tx specific fields.
++ */
++ struct ring_desc *tx_ring;
++ unsigned int next_tx, nic_tx;
++ struct sk_buff *tx_skbuff[TX_RING];
++ u32 tx_dma[TX_RING];
++ u16 tx_flags;
++} npx;
++
++static struct forcedeth_private *np;
++
++static inline void pci_push(u8 * base)
++{
++ /* force out pending posted writes */
++ readl(base);
++}
++static int reg_delay(int offset, u32 mask,
++ u32 target, int delay, int delaymax, const char *msg)
++{
++ u8 *base = (u8 *) BASE;
++
++ pci_push(base);
++ do {
++ udelay(delay);
++ delaymax -= delay;
++ if (delaymax < 0) {
++ if (msg)
++ printf(msg);
++ return 1;
++ }
++ } while ((readl(base + offset) & mask) != target);
++ return 0;
++}
++
++#define MII_READ (-1)
++#define MII_PHYSID1 0x02 /* PHYS ID 1 */
++#define MII_PHYSID2 0x03 /* PHYS ID 2 */
++#define MII_BMCR 0x00 /* Basic mode control register */
++#define MII_BMSR 0x01 /* Basic mode status register */
++#define MII_ADVERTISE 0x04 /* Advertisement control reg */
++#define MII_LPA 0x05 /* Link partner ability reg */
++
++#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
++
++/* Link partner ability register. */
++#define LPA_SLCT 0x001f /* Same as advertise selector */
++#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
++#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
++#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
++#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
++#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
++#define LPA_RESV 0x1c00 /* Unused... */
++#define LPA_RFAULT 0x2000 /* Link partner faulted */
++#define LPA_LPACK 0x4000 /* Link partner acked us */
++#define LPA_NPAGE 0x8000 /* Next page bit */
++
++/* mii_rw: read/write a register on the PHY.
++ *
++ * Caller must guarantee serialization
++ */
++static int mii_rw(struct nic *nic __unused, int addr, int miireg,
++ int value)
++{
++ u8 *base = (u8 *) BASE;
++ int was_running;
++ u32 reg;
++ int retval;
++
++ writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
++ was_running = 0;
++ reg = readl(base + NvRegAdapterControl);
++ if (reg & NVREG_ADAPTCTL_RUNNING) {
++ was_running = 1;
++ writel(reg & ~NVREG_ADAPTCTL_RUNNING,
++ base + NvRegAdapterControl);
++ }
++ reg = readl(base + NvRegMIIControl);
++ if (reg & NVREG_MIICTL_INUSE) {
++ writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
++ udelay(NV_MIIBUSY_DELAY);
++ }
++
++ reg =
++ NVREG_MIICTL_INUSE | (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
++ if (value != MII_READ) {
++ writel(value