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authorAlvaro G. M <alvaro.gamez@hazent.com>2012-03-19 21:56:06 (GMT)
committer Peter Korsgaard <jacmet@sunsite.dk>2012-03-20 13:29:31 (GMT)
commit579e74b150803a51b36831b9d67ab505104a65bb (patch)
tree7be2626e197ce2626114d3961677701b8f2112b3
parentb71aea910eb8c24ba1b9c6a65a6f654ffe171959 (diff)
downloadbuildroot-579e74b150803a51b36831b9d67ab505104a65bb.tar.gz
buildroot-579e74b150803a51b36831b9d67ab505104a65bb.tar.bz2
Config.in.arch: add help and less cryptic names to architecture menu
[Peter: fixup s/big-endian/big endian/ as pointed out by Thomas] Signed-off-by: Alvaro G. M <alvaro.gamez@hazent.com> Acked-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
-rw-r--r--target/Config.in.arch112
1 files changed, 99 insertions, 13 deletions
diff --git a/target/Config.in.arch b/target/Config.in.arch
index 17e0236..a2c0037 100644
--- a/target/Config.in.arch
+++ b/target/Config.in.arch
@@ -8,40 +8,126 @@ choice
Select the target architecture family to build for.
config BR2_arm
- bool "arm"
+ bool "ARM (little endian)"
+ help
+ ARM is a 32-bit reduced instruction set computer (RISC) instruction
+ set architecture (ISA) developed by ARM Holdings. Little endian.
+ http://www.arm.com/
+ http://en.wikipedia.org/wiki/ARM
+
config BR2_armeb
- bool "armeb"
+ bool "ARM (big endian)"
+ help
+ ARM is a 32-bit reduced instruction set computer (RISC) instruction
+ set architecture (ISA) developed by ARM Holdings. Big endian.
+ http://www.arm.com/
+ http://en.wikipedia.org/wiki/ARM
+
config BR2_avr32
- bool "avr32"
+ bool "AVR32"
select BR2_SOFT_FLOAT
+ help
+ The AVR32 is a 32-bit RISC microprocessor architecture designed by
+ Atmel.
+ http://www.atmel.com/
+ http://en.wikipedia.org/wiki/Avr32
+
config BR2_bfin
- bool "bfin"
+ bool "Blackfin"
+ help
+ The Blackfin is a family of 16 or 32-bit microprocessors developed,
+ manufactured and marketed by Analog Devices.
+ http://www.analog.com/
+ http://en.wikipedia.org/wiki/Blackfin
+
config BR2_i386
bool "i386"
+ help
+ Intel i386 architecture compatible microprocessor
+ http://en.wikipedia.org/wiki/I386
+
config BR2_m68k
bool "m68k"
depends on BROKEN # ice in uclibc / inet_ntoa_r
+ help
+ Motorola 68000 family microprocessor
+ http://en.wikipedia.org/wiki/M68k
+
config BR2_microblazeel
- bool "Microblaze AXI (little-endian)"
+ bool "Microblaze AXI (little endian)"
+ help
+ Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
+ based architecture (little endian)
+ http://www.xilinx.com
+ http://en.wikipedia.org/wiki/Microblaze
+
config BR2_microblazebe
- bool "Microblaze non-AXI (big-endian)"
+ bool "Microblaze non-AXI (big endian)"
+ help
+ Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
+ based architecture (non-AXI, big endian)
+ http://www.xilinx.com
+ http://en.wikipedia.org/wiki/Microblaze
+
config BR2_mips
- bool "mips"
+ bool "MIPS (big endian)"
+ help
+ MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
+ http://www.mips.com/
+ http://en.wikipedia.org/wiki/MIPS_Technologies
+
config BR2_mipsel
- bool "mipsel"
+ bool "MIPS (little endian)"
+ help
+ MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
+ http://www.mips.com/
+ http://en.wikipedia.org/wiki/MIPS_Technologies
+
config BR2_powerpc
- bool "powerpc"
+ bool "PowerPC"
+ help
+ PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
+ http://www.power.org/
+ http://en.wikipedia.org/wiki/Powerpc
+
config BR2_sh
- bool "superh"
+ bool "SuperH"
+ help
+ SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
+ instruction set architecture (ISA) developed by Hitachi.
+ http://www.hitachi.com/
+ http://en.wikipedia.org/wiki/SuperH
+
config BR2_sh64
- bool "superh64"
+ bool "SuperH64"
+ help
+ SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
+ instruction set architecture (ISA) developed by Hitachi.
+ http://www.hitachi.com/
+ http://en.wikipedia.org/wiki/SuperH
+
config BR2_sparc
- bool "sparc"
+ bool "SPARC"
+ help
+ SPARC (from Scalable Processor Architecture) is a RISC instruction
+ set architecture (ISA) developed by Sun Microsystems.
+ http://www.oracle.com/sun
+ http://en.wikipedia.org/wiki/Sparc
+
config BR2_x86_64
bool "x86_64"
select BR2_ARCH_IS_64
+ help
+ x86-64 is an extension of the x86 instruction set (Intel i386
+ architecture compatible microprocessor).
+ http://en.wikipedia.org/wiki/X86_64
+
config BR2_xtensa
- bool "xtensa"
+ bool "Xtensa"
+ help
+ Xtensa is a Tensilica processor IP architecture.
+ http://en.wikipedia.org/wiki/Xtensa
+ http://www.tensilica.com/
endchoice
config BR2_microblaze